Boots – shoes – and leggings
Patent
1993-12-22
1996-10-01
Swann, Tod R.
Boots, shoes, and leggings
395822, 395823, 395828, 395869, 39549701, 395401, 395442, 364DIG1, G06F 1310
Patent
active
055618146
ABSTRACT:
A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.
REFERENCES:
patent: 5012408 (1991-04-01), Conroy
patent: 5097437 (1992-03-01), Larson
patent: 5390308 (1995-02-01), Ware et al.
"The Metaflow Architecture", .COPYRGT. 1991 IEEE, Jun. IEEE Micro, Authors: Val Popesuc, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner, David Isaman.
Colwell Robert P.
Fetterman Michael A.
Glew Andrew F.
Hinton Glenn J.
Papworth David B.
Intel Corporation
Peikari J.
Swann Tod R.
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