Methods and apparatus for determining location-based on-chip...

Details Methods and apparatus for determining location-based on-chip... Methods and apparatus for determining location-based on-chip...

2008-07-15

2008-07-15

Dang, Phuc T (Department: 2892)

Semiconductor device manufacturing: process

With measuring or testing

C438S017000, C716S030000

Reexamination Certificate

active

07399648

ABSTRACT:
Techniques for determining a location-based on-chip variation factor for an integrated circuit device are provided. A first on-chip variation factor is computed for at least one of two or more signal paths of the integrated circuit device. The first on-chip variation factor is a function of a timing delay. A second on-chip variation factor is also computed for the integrated circuit device. The second on-chip variation factor is a function of a physical layout of the integrated circuit device. The first on-chip variation factor and the second on-chip variation factor are combined for the at least one of the two or more signal paths to determine a location-based on-chip variation factor for the at least one of the two or more signal paths.

REFERENCES:
patent: 6880133 (2005-04-01), Meyer et al.
patent: 2005/0246117 (2005-11-01), Hathaway et al.
D.G. Chinnery et al., “Closing the Gap Between ASIC and Custom: An ASIC Perspective,” IEEE, Kluwer, pp. 637-642, 2002.
M. Weber, “My Head Hurts, My Timing Stinks, and I Don't Love On-Chip Variation,” SNUG Boston, pp. 1-21, 2002.
M. Orshansky et al., “Impact of Spatial Intrachip Gate Length Variability on the Performance of High-Speed Digital Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 5, pp. 544-553, May 2002.

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