Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2008-07-01
2008-07-01
Lau, Tung S. (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S117000, C702S119000, C702S120000, C702S121000, C702S122000, C702S123000, C702S124000, C702S182000, C702S183000, C714S721000, C438S010000, C438S014000
Reexamination Certificate
active
07395170
ABSTRACT:
A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.
REFERENCES:
patent: 5240866 (1993-08-01), Friedman et al.
patent: 5787190 (1998-07-01), Peng et al.
patent: 6477685 (2002-11-01), Lovelace
patent: 6516309 (2003-02-01), Eberhart
patent: 6787379 (2004-09-01), Madge et al.
patent: 6792373 (2004-09-01), Tabor
patent: 6807655 (2004-10-01), Rehani et al.
patent: 6939727 (2005-09-01), Allen, III et al.
patent: 6943042 (2005-09-01), Madge et al.
Paul E. Black, ed., “run time”, from Dictionary of Algorithms and Data Structures, NIST.
Miguleanez, Emilio et al. “Advanced Automatic Parametric Outlier Detection Technologies for the Production Environment”.
Xu, Li-an, “Statistical Problems in Semiconductor Manufacturing”.
Miller, Russell B. et al. “Unit Level Predicted Yield: a Method of Indentifying High Defect Density Die at Wafer Sort”.
Stanley, James. “Spatial Outlier Methods for Detecting Defects in Semiconductor Devices at Electrical Probe ”.
Sabade, Sagar et a;. “Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification”.
Made, Robert et al, “Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micro Technologies”.
Singh et al., Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study, IEEE.
Singh, Position Statement: Good Die in Bad Neighborhoods, IEEE.
Miller, Position Statement: Good Die in Bad Neighborhoods, IEEE.
Roehr, Position Statement: Good Die in Bad Neighborhoods, IEEE.
Mann, “Leading Edge” of Wafer Level Testing.
Michelson, Statistically Calculating Reject Limits at Parametric Test, IEEE.
Sabade et al., Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Detection, Dept. of Computer Science - Texas A&M University.
Huang, et al., Image Processing Techniques for Wafer Defect Cluster Identification, IEEE.
Sabade, et al., Use of Multiple IDDQ Test Metrics for Outlier Identification, Dept. of Computer Science - Texas A&M University.
Chen, et al., A Neural-Network Approach to Recognize Defect Spatial Pattern in Semiconductor Fabrication, IEEE.
Sapozhnikova, et al., The Use of dARTMAP and Fuzzy Artmap to Solve the Quality Testing Task in Semiconductor Industry, IEEE.
Sikka, Automated Feature Detection & Cahracterization on Sort Wafer Maps.
Hansen, et al., Process Improvement Through the Analysis of Spatially Clustered Defects on Wafer Maps.
Denby, et al., A Graphical User Interface for Spatial Data Analysis in Integrated Circuit Manufacturing, AT&T Bell Laboratories.
Friedman, et al., Model-Free Estimation of Defect Clustering in Integrated Circuit Fabrication.
Hansen, et al., Monitoring Wafer Map Data From Integrated Circuit Fabrication Processes for Spatially Clustered Defects.
Xu, Statistical Problems in Semiconductor Manufacturing.
Thomas Gnieting, Measurement Related and Model Parameter Related Statistics.
Agilent PDQ-WLR(tm) Test and Analysis Software Environment - Product Note, Agilent Technologies, 2000.
Advanced Parametric Tester with HP SPECS, Hewlett-Packard Company, 1999.
Jeff Chappell, LSI Applies Statistics to Defectivity, Apr. 14, 2003 (http://www.reed-electronics.com/electronicnews/index.asp?layout=articlePrint& articleID=CA292185).
Erik Jan Marinissen, et al., Creating Value Through Test, IEEE 2003, 1530-1591.
Russell B. Miller, et al., Unit Level Predicted Yield: a Method of Identifying High Defect Density Die at Wafer Sort, IEEE 2001, 1118-1127.
Philippe LeJeune, et al., Optimizing Yield vs. DPPM for Parts Average Testing, www.galaxysemi.com.
Emilio Miguelanez, et al., Advanced Automatic Parametric Outlier Detection Technologies for the Production Environment.
Guidelines for Part Average Testing, Automotive Electronics Council, AEC-Q001-Rev-C Jul. 18, 2003.
Zinke, Kevin, et al. Yield Enhancement Techniques Using Neural Network Pattern Detection, IEEE 1997, 211-215.
LeJeune, Philippe et al., Minimizing Yield Loss with Parts Average Testing (PAT) and Other DPM Reduction Techniques, Tetradyne Users Group, 2006.
LeJeune, Philippe et al., Minimizing Yield Loss with Parts Average Testing (PAT) and Other DPM Reduction Techniques (Presentation), Tetradyne Users Group, 2006.
Defecter(tm)II - Defect Data Analysis Software, Semicon.
Stanley, James, Spatial Outlier Methods for Detecting Defects in Semiconductor Devices at Electrical Probe, Motorola.
Ratcliffe, Jeff, Setting a Nearest Neighbor IDDQ Threshold.
Daasch, Robert, Variance Reduction Using Wafer Patterns in Iddq Data, Proceeding of International Test Conference Oct. 2000, pp. 189-198.
Daasch, Robert, Neighbor Selection for Variance Reduction in Iddq and Other Parametric Data, ITC International Test Conference, IEEE 2001.
Madge, Robert, et al. Statistical Post-Processing at Wafersort - An Alternative to Burn-In and a Manufacturable Solution to Test Limit Setting for Sub-Micron . . . IEEE 2002.
Motorola, Process Average Testing (PAT), Statistical Yield Analysis (SYA) and Junction Verification Test (JVT), Aug. 3, 1998.
Buxton Paul
Gorin Jacky
Scott Michael J.
Tabor Eric Paul
Kundu Sujoy K
Lau Tung S.
Noblitt & Gilmore LLC
Test Advantage, Inc.
LandOfFree
Methods and apparatus for data analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for data analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for data analysis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2761777