Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-06-14
2002-04-30
Eley, Timothy V. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S007000, C451S053000, C451S285000
Reexamination Certificate
active
06379222
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor manufacture and more particularly to methods and apparatus that employ differential heating of a semiconductor during chemical mechanical planarization of semiconductor wafers.
2. Background of Related Art
In the fabrication of integrated circuits, it is often necessary to polish a side of a part such as a thin flat wafer of a semiconductor material. In general, a semiconductor wafer can be polished to provide a planarized surface to remove topography or surface defects such as a crystal lattice damage, scratches, roughness, or embedded particles such as dirt or dust. This polishing process is often referred to as mechanical planarization or chemical mechanical planarization (“CMP”) and is utilized to improve the quality and reliability of semiconductor devices. The CMP process is usually performed during the formation of various devices and integrated circuits on the wafer.
In general, the chemical mechanical planarization process involves holding a thin flat wafer of semiconductor material against a rotating wetted polishing surface under a controlled downward pressure. A polishing slurry such as a solution of alumina or silica May be utilized as the abrasive medium. A rotating polishing head or wafer carrier is typically utilized to hold the wafer under controlled pressure against a rotating polishing platen. A backing film is optionally positioned between the wafer carrier and the wafer. The polishing platen is typically covered with a relatively soft wetted pad material such as blown polyurethane.
Non-uniformities in polishing rate can result in unwanted irregularities in the semiconductor wafer. Among the factors that can result in non-uniformities in polishing rate are non-uniform distribution of polishing slurry, an unevenly conditioned polishing pad, and an uneven application of pressure to the polishing pad.
A particular problem encountered in the chemical mechanical planarization process is known in the art as the “loading effect”. When the wafer is pressed against a relatively soft polishing pad on the polishing platen of the chemical mechanical planarization apparatus, the polishing pad may deform into the area between the structures to be removed, especially when the polishing rate of the structures is different then the polishing rate of the areas between the structures. This may cause an irregular or wavy surface to be formed on the wafer. In general, this phenomena occurs on the micro level and has an adverse affect on the integrated circuits formed on the wafer, especially in high density applications.
Another example of the loading effect is experienced when a protective or insulating layer of a dielectric material such as, for example, borophosphorus silicate glass, is deposited over transistors formed on a substrate. An initial conformal deposition of the protective layer may produce an irregular surface with peaks directly above the transistors and valleys between the transistors. As before, the polishing pad may deform to accommodate the irregular surface of the protective or dielectric layer. The resultant polished surface may appear on the micro level as wavy or irregular.
The loading effect may function in other situations to remove the sides and base of features present on the surface of a wafer during chemical mechanical planarization. In addition, the loading effect may occur locally or globally across the surface of the wafer. This problem may be compounded by the velocity differential between the outer peripheral portions and the interior portions of the rotating semiconductor wafer. The faster moving peripheral portions of the semiconductor wafer may, for instance, experience a relatively larger rate of material removal than the relatively slower moving interior portions.
In view of the foregoing, there is a need in semiconductor manufacture for a chemical mechanical planarization process that overcomes the loading effect. Accordingly, it is an object of the present invention to provide to lessen or eliminate non-uniformities in polishing rates during CMP.
SUMMARY OF THE INVENTION
It has now been found that providing areas of different temperature on the wafer can be advantageously employed to reduce or eliminate problems of uneven rates of polishing that may be encountered when polishing semiconductor wafers. Specifically, the apparatus described herein include temperature regulating means for increasing the temperature of a first portion of a semiconductor wafer relative to the temperature of a second portion of the semiconductor wafer. The temperature regulating means can cool or heat a desired portion of the semiconductor wafer to provide areas of different temperature on the semiconductor wafer. Methods of polishing semiconductor wafers by providing areas of different temperature on the semiconductor wafer are also described.
REFERENCES:
patent: 5605488 (1997-02-01), Ohashi et al.
patent: 5797789 (1998-08-01), Tanaka et al.
patent: 5882244 (1999-03-01), Hiyama et al.
patent: 5957750 (1999-09-01), Brunelli
patent: 6095898 (2000-08-01), Hennhofer et al.
Hedge Suri G.
Stephens Jeremy Kaspar
Wise Michael Lester
Berry Jr. Willie
Eley Timothy V.
Siemens Aktiengesellschaft
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