Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1998-04-16
2001-12-04
Sheikh, Ayaz (Department: 2155)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
43, C438S018000
Reexamination Certificate
active
06327513
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods and apparatus for calculating alignment of layers during semiconductor processing.
BACKGROUND OF THE INVENTION
Semiconductor devices are typically fabricated by forming a number of layers of material over a wafer and etching such layers to form integrated circuitry features such as conductive lines, resistors, capacitors, interconnect lines, contact openings, and the like. Alignment of overlying layers to underlying layers can be critical, especially as device dimensions continue to shrink.
One approach which has been taken in the past to check wafer alignment during fabrication has been through the use of vernier pattern technology. This technology typically uses patterns comprising a plurality of alignment marks which are formed over one another at different wafer elevations and at different pitches. Misalignments are determined by perceived changes in the overlapping relationship of the patterns from a known overlapping relationship, and quantified by observing the extent to which the patterns' pitch variations cause the patterns to be misaligned. Additional information on alignment technologies can be found in the following references, the disclosures of which are incorporated herein: U.S. Pat. Nos. 4,610,940, 4,742,233, 5,017,514, 5,271,798, 5,545,593, 5,614,446, 5,614,767, 5,633,505, 5,637,186, 5,668,042, and 5,712,063.
This invention arose out of concerns associated with improving the methods and apparatus which are utilized to calculate alignment of layers during semiconductor processing.
SUMMARY OF THE INVENTION
Methods and apparatus for calculating alignment of layers in an integrated circuitry device are described. In one embodiment, a first alignment target is formed over a substrate and includes a pair of first If alignment target edges. A second alignment target is formed over the first alignment target and includes a pair of second alignment target edges. The second alignment target define a point of reference. A first distance is measured between one of the first alignment target edges and one of the second alignment target edges as a first function of the distance from the point of reference. A second distance is measured between the other of the first alignment target edges and the other of the second alignment target edges as a second function of the distance from the point of reference. The first and second functions are differenced to define a linear equation having a slope and an intercept. The intercept contains offset components in two different directions. In a preferred embodiment, a third alignment target is formed over the substrate and a fourth alignment target is formed over the third alignment target and defines a different point of reference. The alignment targets include respective edges, and third and fourth distances are measured between different respective edges of the third and fourth alignment targets as respective functions of the distances from the different point of reference. The third and fourth functions are differenced to define a linear equation having a slope and a second intercept. The second intercept contains offset components in the same two different directions as the first-mentioned intercept. Values are then calculated for the offsets using the first and second intercepts.
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Merriam Webster's Collegiate Dictionary—10thEdition, Principal Copyright 1993, 1 page (p. 842).
Jean Frantz B.
Sheikh Ayaz
VLSI Technology Inc.
Wells, St. John, Roberts, Gregory & Matkin PS
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