Methods and apparatus for caching data in a non-blocking manner

Details Methods and apparatus for caching data in a non-blocking manner Methods and apparatus for caching data in a non-blocking manner

1996-10-15

1997-09-23

Swann, Tod R.

395447, 395403, 395449, 395451, G06F 1300

Patent

active

056714440

ABSTRACT:
A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

REFERENCES:
patent: 5317718 (1994-05-01), Jouppi
patent: 5367660 (1994-11-01), Gat et al.
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 5379396 (1995-01-01), Gochman et al.
patent: 5430888 (1995-07-01), Witek et al.
patent: 5446863 (1995-08-01), Stevens et al.

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