Pulse or digital communications – Receivers – Automatic frequency control
Reexamination Certificate
1998-08-05
2001-05-01
Pham, Chi (Department: 2631)
Pulse or digital communications
Receivers
Automatic frequency control
Reexamination Certificate
active
06226335
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to improvements to wireless receivers. More particularly, the invention relates to the advantageous use of a non-resettable counter for automatic frequency control in wireless receivers.
BACKGROUND OF THE INVENTION
Most wireless receivers employ automatic frequency control (AFC) for the fine tuning of the internal frequency synthesizer to the carrier frequency. In the prior art, the frequency of the carrier is usually measured with a resettable counter, which counts the number of zero-crossings of the input signal over a given period of time. In order to achieve a high accuracy with this method it is necessary to employ a high-order counter. Moreover, reset of the counter introduces a quantization error.
There exists, therefore, a need in the art for a system of automatic frequency control which can be implemented by a lower-order counter and which is not susceptible to quantization error.
SUMMARY OF THE INVENTION
An automatic frequency control system according to the present invention may suitably include a binary N-order non-resettable counter which counts periods of a reference signal. A non-resettable counter rolls over to zero when it reaches its maximum value of 2
N
. A frequency divider generates AFC integration periods inversely proportional to the controlled frequency (proportional to the periods of the controlled signal). A frequency divider includes a resettable counter which counts the number of periods of the controlled frequency and when the number of periods counted matches a stored integration period count value “D”, the resettable counter is reset and the non-resettable counter is read.
Frequency control is advantageously achieved in two (or more) stages. The stages preferably include at least a coarse stage and the fine stage. Switching between the coarse stage and the fine stage is based on an error count computed from the output of the non-resettable counter. The stored frequency divider integration period count value is D. The integration count period D is set based on the error count and controls switching between the coarse stage and the fine stage by controlling how many periods of the controlled frequency must occur between readings of the non-resettable counter. In the coarse stage, the integration period is close to 2
N
*F
REF
, allowing the non-resettable counter to roll over one time during the integration period. In the fine stage, the integration period is close to K*2
N
*F
REF
, where K is an integer greater than 1. Use of the integration period K*2
N
allows the non-resettable counter to rollover K times during the integration period. Frequency error, or count error (‘Error Count’) is computed based on a difference between the current reading of the non-resettable counter and its previous reading. An error correction value ‘Error Correction’ is produced based on the value ‘Error Count’. A new control value ‘Ctrl’ is produced based on the value ‘Error Correction’ and the control value ‘Ctrl’ during the previous AFC cycle. The value ‘Ctrl’ is supplied as a control input to a controlled synthesizer to set the frequency of a controlled signal. The control value is computed according to the following equation:
Ctrl(
n
)=Ctrl(
n−
1)+Correction
Where:
Ctrl(n)=new control value in current AFC cycle
Ctrl(n−1)=control value from the previous AFC cycle
Correction=Correction Value
Correction=[Error Count+Error Correction]*Gain
Where:
Gain=AFC loop gain
Error Count=error computed based on two consecutive readings of the non-resettable counter, as follows
Error Count=
C
(
n
)−
C
(
n−
1)
Where:
C(n)=reading of the non-resettable counter in current AFC cycle
C(n−1)=previous reading of the non-resettable counter
The value ‘Error Correction’ is a constant value for the value ‘Error Count’ computed based on difference of the controlled frequency and the reference frequency and each set of K and D values for each AFC stage, as follows:
Error Correction=(
K*
2
N
−D*F
REF
/F
CTRL
)
Where:
N is the binary order of the non-resettable counter
K is an integer K=1 for the coarse stage, K>1 for fine stage
D is the integration period value of the frequency divider, chosen for each given K to minimize the value ‘Error Correction’.
F
REF
is a reference frequency
F
CTRL
is a desired controlled frequency
Combining all equations above, the value ‘Ctrl’ may be stated as:
Ctrl (
n
)=Ctrl(
n−
1)+[
C
(
n
)−
C
(
n−
1)+(
K*
2
N
−D*F
REF
/F
CTRL
)]*Gain
In cases when non-resettable counter rolls over between two consecutive readings, error count becomes close to 2
N
, such condition is detected by a rollover detector by comparing if the error count is greater than 2
N−1
. In this case, suspension of automatic frequency control is achieved by setting the error count equal to zero.
A more complete understanding of the present invention, as well as further features and advantages of the invention, will be apparent from the following Detailed Description of a presently preferred embodiment and the accompanying drawings.
REFERENCES:
patent: 4485404 (1984-11-01), Tults
patent: 4607230 (1986-08-01), Kaku et al.
Burd Kevin M.
Lucent Technologies - Inc.
Pham Chi
Priest & Goldstein PLLC
LandOfFree
Methods and apparatus for automatic frequency control in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for automatic frequency control in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for automatic frequency control in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2530859