Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-11-30
2001-10-23
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06308192
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates generally to digital processing. More specifically the present invention relates to improved adaptive filtering techniques and architectures as part of that digital processing.
2. The Relevant Technology
Digital processing, and more particularly digital signal processing, is the practice of representing signals with a sequence of numbers and then processing those numbers digitally—often via software—to effect changes to the signal or to extract information from the signal. To a lesser extent, digital processing also creates signals by calculating a sequence of numbers representative of a desired signal waveform.
Some advantages of processing signals in this manner include: consistency, because software does not require tuning as it does not age with time or vary according to temperature; flexibility, because changes to software are more easily implemented than with discrete components; and adaptability, because of the unique nature of software to adapt itself to an incoming signal.
In general, a digital signal processor (DSP) architecture includes an analog-to-digital convertor supplying a digital representation of an input signal to a processor and a digital-to-analog convertor for reconstructing the digital signal back into an analog signal after processing. The digital representation of the input signal is generally a sequence of numbers constructed from discrete time “samples.”
Processing of the digital representation of the input signal by the processor is performed largely by one of three functions, addition, multiplication or delay. Addition and multiplication are generally mathematical functions, whereas delay is generally the processing of a previous sample. All are well known in the art.
Within the processor, as part of the DSP architecture, are digital filters that change the relative amplitudes of various frequency components of the digital signal or eliminate some frequency components entirely. Many filter types exist. Some are adaptive while others are fixed. Yet, most are characterized according to whether their impulse response is finite (FIR) or infinite (IIR). Each has advantages and disadvantages over the other. In general, two design considerations are implicated. They are: (i) how many filter elements or taps are required to achieve a desired frequency response; and (ii) what are the proper coefficient values needed in doing so? FIR filters typically estimate the number of taps needed and then redesign the filter if the taps are too few or too many. IIR filters, on the other hand, usually have fewer taps in comparison to a FIR filter.
With either filter design, the least-means-squares (LMS) algorithm is one of the most widely used methods for achieving an optimized filter design. This algorithm, and its delay counterpart, the delayed LMS (DLMS), are representative of the following discussion. It should be appreciated, however, that other algorithm and methods are also equally applicable.
In general, conventional LMS and DLMS adaptive filters utilize either serial or parallel style architectures. In serial architectures, the digital representation of the input signal, or digital signal, that is being processed is serially passed into and out of the filter. As for engineering considerations, such as pin count and speed of processing the digital signal, the pin count is advantageously low while the speed of processing is disadvantageously slow. Thus, this architecture is not suitable for many high-speed/precision uses.
In contrast, parallel architectures pass the digital signal into and out of the filter in a parallel manner. Thus, the speed of processing is fast but the pin count is high. As such, this architecture is input/output (I/O) bound.
Regardless of whether the architecture is serial or parallel in nature, conventional D/LMS adaptive filters contain numerous filter elements, such as adders, multipliers, etc., for performing the functions of addition, multiplication and delay. During manufacturing, this leads to high economic costs in time and labor. Also, since these elements require large amounts of physical space, silicon costs are high.
Accordingly, it would be an advance to provide improved adaptive filters having the advantages of both serial and parallel architectures without having the disadvantages thereof. In particular, it would advance the present state of the art to have adaptive filters with low pin counts, fast processing times, suitable for high-speed applications, and reduced numbers of filter elements.
OBJECTS AND SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an improved adaptive filter for use in processing digital signals.
It is another object of the present invention to provide an improved adaptive filter architecture suitable for achieving one or all of the following: low pin counts, fast processing times or reduced numbers of filter elements.
It is still another object of the present invention to provide an improved LMS or DLMS adaptive filter suitable for use with a DSP having a VLSI architecture.
It is yet another object of the present invention to provide an adaptive filter having reduced numbers of filter elements and reduced computational complexity for calculating accurate filter coefficients.
It is still yet another object of the present invention to provide an economically improved adaptive filter.
In accordance with the invention as embodied and broadly described herein, the foregoing and other objectives are achieved by providing improved adaptive filtering techniques and architectures. Preferably, this filtering is performed as part of the digital processing that occurs within a digital signal processor. It is a feature of this invention that the adaptive filtering taught herein provides the advantages of both serial and parallel architectures, without the accompanying disadvantages thereof. In particular, an adaptive filter is taught that possesses low pin counts, fast processing times suitable for high-speed applications and reduced numbers of filter elements.
In a preferred embodiment, the inputs and outputs of the adaptive filter are supplied to and from the adaptive filter in a serial manner while the processing is performed internally within the adaptive filter in a parallel manner. The parallel processing is preferably effected by a delayed least-means-squares algorithm implemented using a single adder, a single multiplier and a single multiplier-accumulator.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
REFERENCES:
patent: 4649505 (1987-03-01), Zinser, Jr. et al.
patent: 4771396 (1988-09-01), South et al.
patent: 5001661 (1991-03-01), Corleto et al.
patent: 5245561 (1993-09-01), Sugiyama
3Com Corporation
Malzahn David H.
Workman & Nydegger & Seeley
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