Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2006-10-31
2009-02-10
Potter, Roy K (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S778000
Reexamination Certificate
active
07489026
ABSTRACT:
Methods and apparatus are provided for decreasing the size of Quad Flat No-Lead (QFN) packages (300, 400) down to chip-scale packages. Such QFN packages include a first semiconductor chip (310, 410), a plurality of recessed leads (306, 406, 408, 411) having mold lock features, and a mold material340, 440substantially encasing all sides of the semiconductor chip. An active surface (314, 414) of the semiconductor chip is oriented toward a mounting side (307, 407) of the QFN package, and a plurality of wire bonds330, 430disposed between the active surface and the mounting side couple the active side to the leads. The QFN packages may also include a second semiconductor chip (452) coupled to a plurality of leads (408) and to the first semiconductor chip via wire bonds (431, 432) in a manner similar to the first semiconductor chip.
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McDonald William G.
Wang James J.
Freescale Semiconductor Inc.
Ingrassia Fisher & Lorenz P.C.
Potter Roy K
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