Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
2000-03-30
2002-05-07
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
C438S018000, C324S765010
Reexamination Certificate
active
06383822
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to the manufacture of integrated circuits, and in particular, to a method for testing the quality of integrated circuits during manufacturing.
BACKGROUND INFORMATION
As is well known, the manufacture of integrated circuits (“chips”) is a very expensive process and complicated process. There are numerous ways that a particular chip can be manufactured to have one or more defects, which will degrade the performance of the chip during operations. As such chips proliferate our every day world more and more, it is becoming increasingly imperative that such chips be manufactured with the highest degree of quality.
Various tests are performed on such chips during their manufacturing process, which are used to detect defects and/or predict their potential performance in the field. Such testing methodologies are extremely important in insuring that such parameters as the die-to-ship yield is increased and the parts per million ppm failure rate is minimized.
SUMMARY OF THE INVENTION
The foregoing need is addressed by the present invention, which provides a method to increasing the die-to-ship yield and reducing the parts per million failure rate of chips during their manufacture processes. More specifically, during selected stages of the chip manufacturing process, a test is performed on each of the chips that monitors the chips operating frequency as a function of the selection of a self-timed pulse control (“STPC”) parameter. In an embodiment of the present invention, such frequency measurements are performed on the chips after the STPC parameter has been lowered. This results in the removal of marginal chips from the chip lot in greater numbers than when such frequency measurements are performed at a higher STPC parameter.
An advantage of the present invention is that as a result of the more stringent test requirements, the die-to-ship yield is significantly increased. Not only does this increase customer satisfaction as a result of the increased quality of the shipped chips, but it also saves considerable time and money in insuring that fewer bad chips are packaged.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5818250 (1998-10-01), Yeung et al.
patent: 6057699 (2000-05-01), Yin et al.
patent: 6124143 (2000-09-01), Sugasawara
patent: 6275057 (2001-08-01), Takizawa
Wood, T.J., “The Test and Debug Features of the AMD-K7 Microprocessor”, 1999 IEEE ITC International Test Conference, paper 6.1, pp. 130-136.
Rusk Leland F.
Sprayberry Michael W.
Advanced Micro Devices
Kordzik Kelly K.
Pert Evan
Sherry Michael J.
Winstead Sechrest & Minick P.C.
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