Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
1998-10-02
2001-03-20
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C703S026000
Reexamination Certificate
active
06205414
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to multi-threaded processes in data processing systems utilizing low-end, commodity processors and in particular to emulation of multi-threaded processes in single-threaded operating systems through timer routine interrupts. Still more particularly, the present invention relates to emulating multi-threaded processes in single-thread, single level interrupt operating systems by configuration of a timer interrupt to switch between processes.
2. Description of the Related Art
In many contemporary microprocessor environments, such as those found in consumer electronics, automotive electronics, and industrial controllers, the operating system permits only a single-threaded process. These operating systems are inexpensive since the code for the operating system is relatively easy to implement. By definition, single-threaded processes allow execution only within a single, contiguous code body where operation is strictly sequential. The sequential operation in such an environment typically involves a short, transient flow of one-time operations followed by code looping, where the execution logic continuously polls the state of various external parameters and takes action according to the parameter values.
One problem which occurs is that the need to pursue multi-threaded operations often arises within such an environment after functionality has been developed for a single-threaded operating system. Such needs are normally dealt with either by moving to a multi-threaded operating system and rewriting code for the new operating system or rewriting the single-threaded code body to include the new functionality by recursive calls within the single-threaded limitation. Both approaches require substantial effort in the form of extensive testing to ensure that the desired functionality remains intact. This may not be warranted where the need for true multi-tasking is not required, merely the need to expand the functionality of commodity processors.
It would be desirable, therefore, to provide a system for emulating multi-threaded processes in a single-threaded operating system supporting only single level interrupts.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved method and system for implementing multi-threaded processes in data processing systems utilizing low-end, commodity processors.
It is another object of the present invention to provide a method and system for emulation of multi-threaded processes in single-threaded operating systems through timer routine interrupts.
It is yet another object of the present invention to provide a method and system for emulating multi-threaded processes in single-thread, single level interrupt operating systems by configuration of a timer interrupt to switch between processes.
The foregoing objects are achieved as is now described. To emulate multi-threaded processing in an operating system supporting only single-threaded processes and single-level interrupts, the processor timer is started with a selected time-out period during execution of a master code thread. Processing of the master code thread proceeds until the timer interrupt, at which time the operating system timer interrupt service routine (ISR) transfers execution control to a slave code thread or slave code thread component. The slave code thread or component is executed in its entirety, at which time the timer is reset and execution control is returned to the master code thread, where processing resumes at the point during which the timer interrupt was asserted. To minimize disruption of the master code thread execution, a maximum latency should be enforced on the slave code thread, which may be accomplished by breaking the slave code thread into multiple components. The timer ISR maintains an index of the predetermined starting points within the slave code thread(s) with a pointer identifying the next slave code thread component to be selected when the timer interrupt is asserted. Processing thus alternates between the master code thread and the slave code thread or components, with different slave code thread components being selected in round-robin fashion. The duty cycle between the master code thread and the slave code thread or components may be varied by selection of the time-out period and the maximum latency allowed to slave code thread processing.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Forsman Stephanie Maria
Hamilton, II Rick Allen
Mehta Chetan
Patel Maulin Ishwarbhai
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Jones Hugh
Teska Kevin J.
VanLeeuwen Leslie A.
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