Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2002-05-13
2004-03-16
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S020000, C438S021000, C438S028000, C438S105000, C438S128000, C438S131000, C438S142000, C438S149000, C438S151000, C438S670000, C438S800000
Reexamination Certificate
active
06706566
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to nanostructures, and more particularly to a system and method of electrically induced breakdown of nanostructures.
2. Description of Related Art
In the field of molecular nanoelectronics, few materials show as much promise as nanotubes, and in particular carbon nanotubes, which comprise hollow cylinders of graphite, angstroms in diameter. Nanotubes can be made into tiny electronic devices such as diodes and transistors, depending on the nanotube's electrical characteristics. Nanotubes are unique for their size, shape, and physical properties. Structurally a carbon nanotube resembles a hexagonal lattice of carbon rolled into a cylinder.
Besides exhibiting intriguing quantum behaviors at low temperature, carbon nanotubes exhibit at least two important characteristics: a nanotube can be either metallic or semiconductor depending on its chirality (i.e., conformational geometry). Metallic nanotubes can carry extremely large current densities with constant resistivity. Semiconducting nanotubes can be electrically switched on and off as field-effect transistors (FETs). The two types may be covalently joined (sharing electrons). These characteristics point to nanotubes as excellent materials for making nanometer-sized semiconductor circuits.
Current methods of studying nanotubes rely on the random formation of both metallic and semiconducting nanotubes. There is no known method for reliably preparing a nanotube having particular characteristics, much less for preparing nanotubes to exhibit junctional behavior such as transistors, diodes, etc. Nor are there known methods of nanotube separation by selective synthesis or post-synthesis which have proven to have any measurable level of success. Heretofore, nanotubes must have either been individually separated from mixtures of metallic and semiconducting nanotubes or randomly placed over an electrode to be studied. However, there is no observable consistency in such methods.
This lack of control, compounded by nanotubes tendency to bundle together, has hindered the study of nanotube physics and is seen as a primary roadblock in the nanotube development including nanotube-based electronic technology. Therefore, a need exists for a system and method of preparing nanotubes having desired characteristics.
SUMMARY OF THE INVENTION
A method for forming a device comprises providing a substrate, and providing a plurality of nanotubes in contact with the substrate. The method comprises depositing metal contacts on the substrate, wherein the metal contacts are in contact with a portion of at least one nanotube. The method further comprises selectively breaking the at least one nanotube using an electrical current, removing the metal contacts, and cleaning a remaining nanotube, and depositing a first metal contact in contact with a first end of the nanotube and a second metal contact in contact with a second end of the nanotube.
The method further comprises connecting a first metal contact of a first device to a first metal contact of a second device, connecting a substrate of the first device with a substrate of a second device, connecting a second metal contact of the first device to a first voltage, and connecting a second metal contact of the second device to a second voltage. The first device is a p-type field effect transistor and the second device is an n-type field effect transistor. The method comprises depositing a resist over the n-type field effect transistor. The method comprises providing an external potential to the substrate of the first device and the substrate of the second device.
The method further comprises the step of depleting a semiconducting nanotube of a plurality of carriers. Depleting a semiconducting nanotube of a plurality of carriers further comprises the step of applying a voltage to a gate electrode on the substrate. The method comprises applying the electrical current through the nanotube from a source electrode to a drain electrode.
The plurality of nanotubes are multi-walled nanotubes including metallic and semiconducting nanotubes. The plurality of nanotubes are single-walled nanotube ropes including metallic and semiconducting nanotubes.
The substrate is an insulator and includes an array of metallic pads. The substrate is silica based and includes the array of metallic pads. Each pad includes one of a source electrode, a drain electrode, and a gate electrode.
Providing a substrate is accomplished using lithography to form an array of pads, each pad including a corresponding electrode on an insulating substrate.
The nanotubes are carbon nanotubes.
The method comprises breaking a plurality of stray nanotubes.
A method for forming a p-type field effect transistor device comprising providing an insulating substrate, and providing a plurality of carbon nanotube bundles including metallic and semiconducting component nanotubes in contact with the substrate. The method comprises breaking the carbon nanotube bundles, cleaning carbon nanotube bundles, and depositing a resist over a portion of the device, wherein a portion of the carbon nanotube bundles is exposed. The method further comprises exposing the portion of the carbon nanotube bundles to a gas, depositing a plurality of metal contacts, and removing the resist. The method deposits a gate oxide over the device, and deposits a top gate metal contact.
The gas modifies the conformation of the nanotube to behave as a p-type nanotube.
The method comprises connecting the p-type field effect transistor device to an n-type field effect transistor device to form an inverter device.
The p-type field effect transistor is formed on a first substrate and the n-type field effect transistor is formed on a second substrate. The p-type field effect transistor and the n-type field effect transistor are formed on the same substrate.
A method for forming an n-type field effect transistor device comprises providing an insulating substrate, providing a plurality of carbon nanotube bundles including metallic and semiconducting component nanotubes in contact with the substrate, and breaking the carbon nanotube bundles. The method further comprises cleaning carbon nanotube bundles, depositing a resist over a portion of the device, wherein a portion of the carbon nanotube bundles is exposed, and annealing the device. The method comprises depositing a plurality of metal contacts, removing the resist, and annealing the device to form n-type nanotubes. The method further comprises depositing a gate oxide over the device, and depositing a top gate metal contact.
Annealing the device is implemented in one of a vacuum and an inert gas.
The method comprises connecting the n-type field effect transistor device to an p-type field effect transistor device to form an inverter device.
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U.S. patent application Publication No. US 2002/0020841 A1, published Feb. 21, 2002,Carbon Nanotube Device, Ji Soon Ihm.
Sander J. Tans, et al.,Room-temperature transistor based on a Single Carbon Nanotubes, Nature, vol. 393, May 7, 1998, pp. 49-52.
Per Hyldgaard et al.,Robust Nanosized Transistor Effect in Fullerene-Tube Heterostructure, Department of Applied Physics, Chalmers University of Technology and Goteborg University, Goteborg, Sweden, Nov. 7, 2000.
V. Derycke et al.,Carbon Nanotubes Inter and Intramolecular Logic Gates, Nanoletters, vol. 1, No. 9, Sep. 2001 (received Aug. 16, 2001).
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Avouris Phaedon
Collins Philip G.
Derycke Vincent Stephane
Martel Richard
Cuneo Kamand
F. Chau & Associates LLP
Kilday Lisa
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