Methodology for deriving executable low-level structural descrip

Details Methodology for deriving executable low-level structural descrip Methodology for deriving executable low-level structural descrip

1990-04-06

1993-06-22

Trans, Vincent N.

Boots, shoes, and leggings

364488, 364578, G06F 1560

Patent

active

052220303

ABSTRACT:
A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.

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"An Efficient Heuristic Procedure for Partitioning Graphs" by B. W. Kermghan et al., The Bell System Technical Journal; Feb. 1970, pp. 291-307.

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