Methodology and graphical user interface for building logic...

Details Methodology and graphical user interface for building logic... Methodology and graphical user interface for building logic...

1999-01-11

2004-02-24

Follansbee, John (Department: 2126)

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

C345S215000, C717S105000, C716S030000

Reexamination Certificate

active

06697880

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a micro-template graphical user interface (GUI) and methodology that enables the user of a script-oriented logic synthesis tool to break a template for a logic synthesis command script into smaller and functionally independent templates termed “micro-templates.”
2. Description of the Related Art
With astonishing regularity over the past several decades, transistors have become smaller and the devices that employ them have become more complex. Today it is not uncommon for an integrated circuit (IC) to contain millions of transistors. The job of designing these ICs has also grown correspondingly more difficult. What was once accomplished by a single individual or a small group of individuals is typically performed by a large team or multiple teams of designers.
Although microprocessors and microcontrollers have become more difficult to design, a number of tools have been developed to make the job easier. One class of tools that makes the job more manageable is called electronic design automation (EDA). Using an EDA tool, a designer can break a large circuit into smaller functional units and specify constraints and requirements such as desired inputs and outputs of the functional units. The EDA tool then suggests solutions, often drawing on a vast digital library of possible circuits. In this manner, large circuits are decomposed into more manageable units that can be designed individually, perhaps by groups of designers working more or less independently. The result is that the overall design process is significantly faster than it would be otherwise.
A design framework may provide a graphical synthesis environment in which a designer can constrain and synthesize a design using a set of templates for creating logic synthesis command scripts. Information relevant to a specific design may be stored in template files and compiled into a design run as needed. The design framework may provide a mechanism for maintaining and sharing synthesis scripts and parameters. Also, the design framework may enable a user to create a gate-level netlist (a shorthand description of a schematic indicating connections among logic elements) including Design For Test (DFT) scan chains. For example, a synthesis page of a design framework may allow a user to configure synthesis constraints, compile high-level Register Transfer Level (RTL) code which takes into account the constraints, generate data for other teams of designers who place and route the design in light of the constraints, and generate schematics used for final circuit layout configuration. Certain design frameworks thus have given a user the ability to easily constrain and synthesize a design using a known set of synthesis templates.
Typically, EDA and DFT tools are command oriented, with the data required to set up and compile a design contained within a logic synthesis command script. A logic synthesis command script contains the commands necessary to run an EDA tool as well as the commands necessary to locate and read the required data files. Logic synthesis command scripts may be generated by use of logic synthesis templates. A logic synthesis template is a skeleton script that provides a form to follow in the generation of the command script, making the generation of the script easier.
Logic synthesis command scripts generate extremely long run times due to their complex nature. Typically, the command script initiates a compiler that processes both the data contained within the data files and information contained in design libraries to generate the output such as netlists, schematics and reports. When the data files increase in size, the necessary processing grows exponentially. As microprocessors, microcontrollers, and dedicated integrated circuits grow larger and more complex, the EDA tools and the compilers that design these circuits become more and more taxed to perform their tasks.
SUMMARY OF THE INVENTION
Briefly, a system according to the present invention employs a graphical user interface (GUI) to enable a synthesis user to build and run logic synthesis command scripts tailored to a task at hand. By means of the GUI, the synthesis user can concentrate on particular synthesis operations by enabling certain synthesis operations and disabling other synthesis operations. The particular synthesis operations are defined by use of “micro-templates.” A template constructed from selected micro-templates may include desired synthesis fuctionality and exclude undesired synthesis functionality. By selectively limiting the synthesis operations that a compiler has to process, the compiler can work faster and more efficiently. Micro-templates thus bring a new degree of flexibility and proficiency to logic synthesis.
A disclosed GUI is a build script graphical user interface to selectively enable and disable micro-templates. The build script GUI includes a Create script option to build a logic synthesis command script corresponding to enabled micro-templates. In the past, to debug logic synthesis whether through manual or script-based commands, it was necessary to resynthesize for virtually all synthesis operations. The time to do so was prohibitive. In accordance with the present invention, by using the build script GUI to enable only the synthesis operations of debug interest, synthesis time may be significantly reduced.


REFERENCES:
patent: 5657438 (1997-08-01), Wygodny et al.
patent: 5675752 (1997-10-01), Scott et al.
patent: 5854930 (1998-12-01), McLain et al.
patent: 5862372 (1999-01-01), Morris et al.
patent: 6002868 (1999-12-01), Jenkins et al.
patent: 6006230 (1999-12-01), Ludwig et al.
patent: 6043815 (2000-03-01), Simonoff et al.
patent: 6046742 (2000-04-01), Chari
patent: 6054983 (2000-04-01), Simonoff et al.
patent: 6182279 (2001-01-01), Buxton
patent: 6212674 (2001-04-01), Suckow
patent: 6247020 (2001-06-01), Minard
patent: 6311320 (2001-10-01), Jibbe
patent: 6321369 (2001-11-01), Heile et al.
patent: 6378123 (2002-04-01), Dupenloup
patent: 6425116 (2002-07-01), Duboc et al.
patent: 6591272 (2003-07-01), Williams
patent: 2003/0027561 (2003-02-01), Iyer
Neuron Data, Inc. “Ooscript Language” Technical Paper. Apr. 2, 1996.*
Design Compiler, Release 1998.02, Synopsys, Inc., © 1998.
Silicon Arena User Guide—Project Setup, Unified Design Automation, Inc., © 1995-98, pp. 1-15, <http:\\www.udai.com/help/ProjectEdit.shtml>(last modified Feb. 12, 1999).
Silicon Arena User Guide—Synthesizing Designs, Unified Design Automation, Inc., © 1995-1998, pp. 1-9, <http:\\www.udai.com/help/SynthesizingDesigns.shtml>(last modified).

Affiliated with

Also associated with

Rating

Methodology and graphical user interface for building logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methodology and graphical user interface for building logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methodology and graphical user interface for building logic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3307787