Methodology and applications of timing-driven logic...

Details Methodology and applications of timing-driven logic... Methodology and applications of timing-driven logic...

2007-05-15

2007-05-15

Knight, Anthony (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C716S030000

Reexamination Certificate

active

09754406

ABSTRACT:
Aspects of the present invention include a methodology for the general timing-driven iterative refinement-based approach, a timing-driven optimization (TDO) method that optimizes the circuit depth after the area oriented logic optimization, and a layout-driven synthesis flow that integrates performance-driven technology mapping and clustering with TDO to account for the effect of mapping and clustering during the timing optimization procedure of TDO. The delay reduction process recursively reduces the delay of critical fanins of a selected. Furthermore, in one embodiment, the fanins of the selected node are sorted according to their slack values.

REFERENCES:
patent: 5648913 (1997-07-01), Bennett et al.
Singh, K.J., Performance Optimization of Digital Circuits, Ph.D. Dissertation, University of California Berkley, 1992.
Singh et al, “Timing Optimization of Combinational Logic”, Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference, Nov. 7-10, 1988, pp. 282-285.
Huang et al, “An Iterative Area/Performance Trade-Off Algorithm for LUT-Based FPGA Technology Mapping” Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on , Nov. 10-14, 1996 pp. 13-17.
Singh et al, “A Heuristic Algorithm for the Fanout Problem”, 27th ACM/IEEE Design Automation Conference, 1990, pp. 357-360.
Ju et al “Incremental Techniques for the Identification of Statistically Sensitizable Critical Paths”, 28th ACM/IEEE Design Automation Conference, Paper 32.2, pp. 541-546, 1991.
Chen et al., Combining Technology Mapping and Placement for Delay-Optimization in FPGA Designs 1993 Unvi. of Tsing Hua IEEE p. 123-127.
Cong et al., “Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs” 1998 ACM p. 704-707.
Murgai et al., “Performance Directed Synthesis for Table Look Up Programmable Gate Arrays” 1991 IEEE p. 572-575.
Changfan et al., “Timing Optimization on Routed Design with Incremental Placement and Routing Characterization” 2000 IEEE p. 188-196.
Singh, K.J., Performance Optimization of Digital Circuits, Ph.D. Dissertation, pp. 33-79, University of California at Berkeley, 1992.
Pan, P., Performance-Driven Integration of Retiming and Resynthesis, in Proc. Design Automation Conf., pp. 243-246, 1999.
Tamiya, Y., Performance Optimization Using Separator Sets, in Proc. Int'l Conf. On Computer Aided Design, pp. 191-194, 1999.
Sentovich et al., SIS: A System for Sequential Circuit Synthesis, Electronics Research Laboratory, Memorandum No. UCB/ERL M92/41, 1992.
Hwang, Y.-Y., Logic Synthesis for Lookup-Table Based Field Programmable Gate Arrays, Ph.D. Dissertation, pp. 35-63, University of California at Los Angeles, 1999.
Yang, S., Logic Synthesis and Optimization Benchmarks User Guide Version 3.0, Technique Report, MCNC, Jan. 1991.
Songjie Xu,Synthesis for High-Density and High-Performance FPGAs,dissertation submitted to University of California, Los Angeles, Aug. 31, 2000.
Singh, Kanwar Jit, Ph.D.,Performance Optimization of Digital Circuits,dissertation submitted to University of California, Berkeley, 1992.

Affiliated with

Also associated with

Rating

Methodology and applications of timing-driven logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methodology and applications of timing-driven logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methodology and applications of timing-driven logic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3775484