Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2000-01-26
2002-04-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S478000
Reexamination Certificate
active
06372518
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to the fabrication of layered superlattice materials, and more particularly to a fabrication method using unreactive gas annealing and a low temperature pretreatment to reduce exposure of an integrated circuit to oxygen at elevated temperature.
2. Statement of the Problem
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See Miller, U.S. Pat. No. 5,046,043. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Layered superlattice material oxides have been studied for use in integrated circuits. U.S. Pat. No. 5,434,102, issued Jul. 18, 1995, to Watanabe et al., and U.S. Pat. No. 5,468,684, issued Nov. 21, 1995, to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits. Layered superlattice materials exhibit characteristics in ferroelectric memories that are orders of magnitude superior to alternative types of ferroelectric materials, such as PZT and PLZT compounds.
Integrated circuit devices containing ferroelectric elements with layered superlattice materials are currently being manufactured. A typical ferroelectric memory cell in an integrated circuit contains a semiconductor substrate and a metaloxide semiconductor field-effect transistor (“MOSFET”) in electrical contact with a ferroelectric device, usually a ferroelectric capacitor. A ferroelectric memory capacitor typically contains a thin film of ferroelectric metal oxide located between a first, bottom electrode and a second, top electrode, the electrodes typically containing platinum. Layered superlattice materials comprise metal oxides. In conventional fabrication methods, crystallization of the metal oxides to produce desired electronic properties requires heat treatments in oxygen gas at elevated temperatures. The heating steps in the presence of oxygen are typically performed at a temperature in the range of from 800° C. to 900° C. for 30 minutes to two hours. As a result of the presence of reactive oxygen at elevated temperatures, numerous defects are generated in the single crystal structure of the semiconductor silicon substrate, leading to deterioration in the electronic characteristics of the MOSFET. Good ferroelectric properties have been achieved in the prior art using process heating temperatures at about 700° C. to crystallize layered superlattice material. See U.S. Pat. No. 5,508,226, issued Apr. 16, 1996, to Ito et. al. Nevertheless, the annealing and other heating times in the low-temperature methods disclosed in the prior art are in the range of three to six hours, which may be economically unfeasible. More importantly, the long exposure time of several hours in oxygen, even at the somewhat reduced temperature ranges, results in oxygen damage to the semiconductor substrate and other elements of the CMOS circuit.
After completion of the integrated circuit, the presence of oxides may still cause problems because oxygen from the thin film tends to diffuse through the various materials contained in the integrated circuit and combine with atoms in the substrate and in semiconductor layers forming oxides. The resulting oxides interfere with the function of the integrated circuit; for example, they may act as dielectrics in the semiconducting regions, thereby virtually forming capacitors. Diffusion of atoms from the underlying substrate and other circuit layers into the ferroelectric metal oxide is also a problem; for example, silicon from a silicon substrate and from polycrystalline silicon contact layers is known to diffuse into layered superlattice material and degrade its ferroelectric properties. For relatively low-density applications, the ferroelectric memory capacitor is placed on the side of the underlying CMOS circuit, and this may reduce somewhat the problem of undesirable diffusion of atoms between circuit elements. Nevertheless, as the market demand and the technological ability to manufacture high-density circuits increase, the distance between circuit elements decreases, and the problem of molecular and atomic diffusion between elements becomes more acute. To achieve high circuit density by reducing circuit area, the ferroelectric capacitor of a memory cell is placed virtually on top of the switch element, typically a field-effect transistor (hereinafter “FET”), and the switch and bottom electrode of the capacitor are electrically connected by a conductive plug. To inhibit undesired diffusion, a barrier layer is located under the ferroelectric oxide, between the capacitor's bottom electrode and the underlying layers. The maximum processing temperature allowable with current barrier technology is in the range of from 700° C. to
750
° C. At temperatures above this range, the highest-temperature barrier materials begin to degrade and lose their diffusion-barrier properties. On the other hand, the minimum feasible manufacturing process temperatures of layered superlattice materials used in the prior art is about 800° C., which is the temperature at which deposited layered superlattice materials are annealed to achieve good crystallization. Lower annealing temperatures require much longer time periods of exposure to oxygen, which can result in damage to the integrated circuit.
For the above reasons, therefore, it would be useful to have a method for fabricating layered superlattice materials in ferroelectric integrated circuits that minimizes the time of exposure to oxygen at elevated temperature, as well as reduces the maximum temperature used.
SUMMARY OF THE INVENTION
The embodiments of the present invention reduce the time of exposure of the integrated circuit to oxygen gas at elevated temperature, and reduce fabrication processing temperatures.
In an important embodiment of the invention, a portion of the time period during which an integrated circuit is heated or annealed at elevated temperature is conducted in an oxygen-free unreactive gas. The oxygen-free gas may be any relatively unreactive gas or mixture of unreactive gases, such as nitrogen and the noble gases, in particular, argon and helium. A useful result of embodiments of the invention is that when a fabrication method includes annealing in unreactive gas for a significant portion of the total annealing time at elevated temperature, then the ferroelectric polarizability of layered superlattice material is as high or higher than the polarizability of layered superlattice material annealed for the same total annealing time in oxygen only.
The invention provides a method of fabricating a thin film of layered superlattice material comprising: providing a substrate and a precursor containing metal moieties in effective amounts for spontaneously forming a layered superlattice material; applying the precursor to the substrate; annealing the solid thin film in an unreactive gas at a temperature in a range of from 600° C. to 800° C.; and annealing the solid thin film in an oxygen-containing gas at a temperature in a range of from 600° C. to 800° C. The invention contemplates that the annealing in an unreactive gas may either precede or come after the annealing in an oxygen-containing gas. The annealing in an unreactive gas may be conducted for a time period in the range of from 30 minutes to 100 hours. The annealing in an oxygen-containing gas is conducted for a time period in the range of from 30 minutes to two hours. In a preferred embodiment, the annealing in an oxygen-containing gas is conducted for a time period not exceeding 60 minutes. Typically, this step of annealing is conducted in substantially pure O
2
gas.
A further embodiment of the invention includes heating the substrate after applying the precursor, forming a solid film from the precursor. In an embodiment, the heating is conducted at a temperature not exceeding 600° C. The heating typically co
Arita Koji
Nasu Toru
LandOfFree
Method using unreactive gas anneal and low temperature... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method using unreactive gas anneal and low temperature..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method using unreactive gas anneal and low temperature... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2840299