Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-04
2003-05-13
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S063000, C365S185220
Reexamination Certificate
active
06563742
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a multiple time programmable (MTP), electrically programmable read-only memory (EPROM) device, and more particularly, to a MTP EPROM formed using Flash memory cells.
(2) Description of the Prior Art
For over twenty years, EPROM devices have been used extensively in numerous applications. Traditional EPROM devices come in two package configurations. The first configuration is a ceramic package with a quartz window. The second configuration is a plastic package without a quartz window. The reason for using the more expensive package with the quartz window is to provide for multiple time programmability (MTP) of the EPROM. The memory cell array in the EPROM is erased by exposure to ultraviolet (UV) light through the window. The EPROM memory data becomes all “1” after the UV light erase, regardless of the initial data value (“0” or “1”). During programming, the EPROM data is selectively altered from the erased state (“1”) to the programmed state (“0”) through an electrical operation controlled by a programmer. In the plastic packages, for example, plastic dual in-line package (PDIP or simply, DIP) and plastic leaded chip carrier (PLCC), the absence of the quartz window eliminates the possibility of MTP. Therefore, these EPROM devices are said to be one-time programmable (OTP).
Referring now to
FIG. 1
, an exemplary, functional block diagram of a prior art EPROM is illustrated. A cell array
10
comprises standard EPROM cells. These EPROM cells may comprise devices that can store electrical charge on a floating gate. This electrical charge, in turn, alters the threshold voltage of the devices such that the devices are always in either of two, distinctive states. These states are conveniently labeled as the “0” state. and the “1” state. As stated previously, the EPROM cells are electrically programmable from the erased (“1”) state to the programmed (“0”). To accomplish this programming, a high voltage signal must be routed to the specific cell that is selected for programming. This high voltage signal, called the positive programming voltage (VPP), is an external signal in the JEDEC standard configurations.
Access to the cell array
10
is controlled by a control logic block
14
. The control logic block uses the input signals, chip enable bar (CEB), output enable bar (OEB), and program enable bar (PGMB). CEB is asserted by a low voltage (V
il
) to cause the EPROM memory to be selected. OEB is asserted by a low voltage, V
il
, to cause the output data bus, DQn-DQ
0
, to be driven. PGMB is an optional signal that is asserted by a low voltage, V
il
, to cause the EPROM to enter programming mode. Note that the OEB and VPP signals may be multiplexed onto the same input pin since the VPP signal is active at a high voltage of, for example, about 12 volts.
When the EPROM is selected by an assertion of CEB, the value of the address bus An-A
0
is latched by the address buffers block
18
. The address value is then used by the X-Decoder block
26
and the Y-Decoder block
30
to select a specific byte or word within the cell array
10
. If the EPROM is being read from, then the OEB signal will be asserted. In this case, the value of the selected byte or word of the memory cell array
10
is presented at the output data bus, DQn-DQ
0
, by the output buffers block
22
. If the EPROM is being written to, the OEB signal will not be asserted. The PGMB signal will be asserted. In this case, the value of the selected byte, or word, which has been externally forced onto the data bus, DQn-DQ
0
, will be written at the selected memory cell array location.
The prior art EPROM device has no provision for electrical erasure of the memory cell array
10
. Only the exposure to UV light, and the requisite expensive packaging, can be used for erasure. In addition, as the EPROM device size and density grows larger, this UV light erase technique may be severely degraded because the UV light. may not be able to reach all of the floating gates in the very small cells.
Referring now to
FIGS. 2 through 9
, JEDEC standard pin configurations for the most popular, prior art OTP EPROM devices are shown for DIP and PLCC packages. The memory sizes vary between 64 kilobits and 8 megabits. Although the OTP EPROM pin configurations vary with different memory storage capacity, or density, all follow the universal, joint electron device engineering council (JEDEC) standards. Referring particularly to
FIG. 2
, the JEDEC standard configurations for a 64 kilobit part are shown. The DIP package is a 28-pin part. The PLCC package is a 32-pin part. Note that the VPP signal has a separate pin from the OEB signal. In addition, the PGMB signal is available. Referring to
FIG. 3
, a 128 kilobit part is shown. Again, VPP is separate from OEB, and PGMB is available.
Referring to
FIG. 4
, the 256 kilobit part is shown. The key difference at this density is the loss of the PGMB pin. Referring now to
FIG. 5
, the 512 kilobit part is shown. At this density, the JEDEC standard configuration moves the VPP signal to the same pin as the OEB signal. The VPP signal and OEB signal are multiplexed together.
Referring now to
FIG. 6
, the 1 megabit EPROM device is shown. The DIP part pin count increases to 32 pins. The PLCC package remains at 32 pins. With the extra pins, the 1 megabit device provides separate VPP and OEB pins as well as a PGMB pin. Referring now to
FIG. 7
, the 2 megabit EPROM device also provides separate VPP and OEB pins and a PGMB pin.
Referring now to
FIG. 8
, the 4 megabit OTP EPROM removes the PGMB pin. Finally, referring to
FIG. 9
, the 8 megabit EPROM combines VPP and OEB as a multiplexed pin.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective, and very manufacturable, multiple time programmable (MTP) EPROM device conforming to JEDEC EPROM pin configuration standards.
A further object of the present invention is to provide a MTP EPROM using a Flash memory cell array.
A still further object of the present invention is to provide a MTP EPROM based on a Flash memory cell array in which cost is reduced by eliminating the internal charge pumps and state machine.
Another still further object of the present invention is to provide a MTP EPROM based on a Flash memory cell array in which an external, negative erasing voltage (VNN) pin is used.
Another still further object of the present invention is to multiplex an external, negative erasing voltage (VNN) pin with an existing pin.
Another still further object of the present invention is to provide a MTP EPROM based on a Flash memory cell array with threshold voltage (V
t
) correction capability.
Another further object of the present invention is to provide a method for erasing a MTP EPROM.
Another further object of the present invention is to provide a method for programming a MTP EPROM.
Another further object of the present invention is to provide a method for correcting the threshold voltage (V
t
) of a MTP EPROM.
In accordance with the objects of this invention a multiple time programmable memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. A package has an external pin configuration that conforms to the JEDEC standard for an EPROM device wherein an external, positive programming voltage (VPP) pin is provided. Finally, an external, negative erasing voltage (VNN) pin is provided.
Also in accordance with the objects of the present invention, a method to electrically erase a multiple time programmable device is achieved. The multiple time programmable device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. A package has a pin configuration that conforms to the JEDEC standard for an EPROM device and has an external, positive programming voltage (VPP) pin. Finally, an external, negative erasing voltage (VNN) pin is multiplexed with a chip enable bar (CEB) pin. The method comprises, first, as
Lee Peter W.
Tran Tam H.
Ackerman Stephen B.
Aplus Flash Technology Inc.
Nguyen Tan T.
Saile George O.
Schnabel Douglas R.
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