Method to solve holes in passivation by metal layout

Details Method to solve holes in passivation by metal layout Method to solve holes in passivation by metal layout

1994-07-25

1996-02-27

Fourson, George

Fishing, trapping, and vermin destroying

437235, 437245, 148DIG137, H01L 2144

Patent

active

054948533

ABSTRACT:
A new method of forming the passivation layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed having a metal line layout in which the metal lines have a fixed spacing throughout their length and larger width around a turn than they have throughout the remainder of their length. Metal islands are formed perpendicular to the metal lines at the terminals of the metal lines. Dummy vias are opened in the insulating layer at the terminals of the metal lines wherein the terminals of the metal lines fill the dummy vias thereby reducing the aspect ratio of the spacing of said metal lines. A passivation layer is deposited over the metal lines wherein tunnels are formed within the passivation layer between the metal lines and at the terminals of the metal lines. The metal layout of the present invention prevents openings from being made within the passivation layer to the tunnels. The passivation layer is covered with a resist layer. The resist layer has a relatively constant thickness because the resist does not sink into the tunnels. The passivation layer is patterned. Holes are not formed within the passivation layer because of the relatively constant thickness of the resist layer.

REFERENCES:
patent: 5032890 (1991-07-01), Ushiku et al.
patent: 5441915 (1995-08-01), Lee

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