Method to reveal the architecture of multilayer interconnectors

Details Method to reveal the architecture of multilayer interconnectors Method to reveal the architecture of multilayer interconnectors

1997-06-02

1999-08-03

Chaudhuri, Olik

Semiconductor device manufacturing: process

With measuring or testing

438622, 438637, 438710, H01L 2100

Patent

active

059337044

ABSTRACT:
A new method of preparing for inspection a wafer having multilayer interconnections is described. Semiconductor device structures having multilayer interconnections are provided in and on a semiconductor substrate wherein the multilayer interconnections comprise alternating layers of oxide interlevel dielectric layers and conducting layers and wherein interconnections are made between the conducting layers through the interlevel dielectric layers and wherein a non-oxide passivation layer overlies the topmost dielectric layer. The non-oxide passivation layer is removed and an oxide passivation layer is deposited overlying the topmost dielectric layer. The oxide passivation layer and interlevel dielectric layers and conducting layers are cut through to expose a sidewall to reveal the multilayer interconnections. The interlevel dielectric layers between conducting layers in the area of the exposed sidewall are removed to complete preparation for observing the semiconductor wafer having multilayer interconnections.

REFERENCES:
patent: 4900695 (1990-02-01), Takahashi et al.
patent: 5028780 (1991-07-01), Kaito et al.
patent: 5413962 (1995-05-01), Lur et al.
patent: 5583344 (1996-12-01), Mizumura et al.

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