Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-19
2001-08-28
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S296000, C438S700000
Reexamination Certificate
active
06281093
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor devices, and more particularly, to the reduction of trench cones in the fabrication of trenches in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
The use of shallow trench isolation (STI) for the formation of integrated circuit isolations has grown in the art due to the reduced surface area and improved topology of STI when compared to traditional local oxidation of silicon (LOCOS) schemes. One problem that is encountered in the use of STI is the formation of trench cones during the trench etching process.
Referring to
FIG. 1
, a cross-section of a partially completed prior art integrated circuit is shown. A semiconductor substrate
10
is shown. A silicon dioxide, or pad oxide, layer
14
overlies the semiconductor substrate
10
. A silicon nitride layer
18
overlies the silicon dioxide layer
14
. The silicon nitride layer
18
and the silicon dioxide layer
14
are patterned to thereby expose the semiconductor substrate
10
where shallow trench isolations are planned. The silicon nitride layer
18
forms a hard mask for the subsequent trench etching.
Note that a residue of passive surface material
22
overlies the semiconductor substrate
10
after the patterning step. This passive surface material
22
may comprise silicon nitride or silicon dioxide residue that remains after the hard mask is etched. In addition, the passive surface material
22
may comprise native oxide or another material.
Referring now to
FIG. 2
, the trench for the STI is etched into the semiconductor substrate
10
. The trench etching process uses the silicon nitride layer
18
as a hard mask. During the etching process, trench cones
26
, also called silicon cones
26
, are formed. The presence of the passive surface material
22
inhibits substrate etching and thereby causes the formation of these cones
26
. The gases used in the dry etching process are not able to remove this passive surface material
22
. The presence of the cones
26
within the trench is detrimental to the isolation performance of the STI.
Several prior art approaches disclose methods to form shallow trench isolation in the semiconductor substrate. U.S. Pat. No. 4,534,824 to Chen discloses a method to form STI with improved surface inversion immunity. The oxide-nitride-oxide layer overlying the substrate is patterned to expose the substrate where a trench is planned. Stop junctions are implanted into the substrate. The junctions are laterally diffused beyond the opening boundary by heat treatment. Sidewall spacers are formed on the oxide-nitride-oxide layer to narrow the opening. The substrate is then etched through the opening. The laterally diffused part of the stop junctions remains after the trench etch. U.S. Pat. No. 5,780,353 to Omid-Zohoor teaches a method to form STI with doped sidewalls. The silicon nitride layer overlying the substrate is patterned to expose the substrate where trenches are planned. Ions are implanted through the opening to form a junction. The junction is laterally diffused beyond the opening boundary by heat treatment. The trench is etched into the substrate. The doped junction rims the top of the trench. U.S. Pat. No. 5,118,636 to Hosaka discloses a method to form STI. The oxide layer overlying the substrate is patterned to expose the substrate. Ions are implanted through the opening to form a doped junction. An anneal is performed to laterally diffuse the doped junction beyond the opening boundary. The trench is etched into the substrate through the opening. The doped junction thereby surrounds the top of the trench. U.S. Pat. No. 5,668,044 to Ohno teaches a method to form STI. An insulator layer that overlies the substrate is patterned to expose the substrate where the trench is planned. Ions are implanted through the opening to form a doped junction. An anneal is performed to laterally-diffuse the junction beyond the opening boundary. The trench is etched through the opening and a stopping junction is thereby formed surrounding the top of the trench. U.S. Pat. No. 6,004,864 to Huang et al discloses a method to form STI. An insulator layer that overlies the substrate is patterned to expose the substrate where the trench is planned. Ions are implanted through the opening to form a heavily-doped junction in the substrate. A rapid thermal anneal (RTA) is performed to activate the implanted ions. An aqueous HF wet etch is performed to etch the trench. The presence of the heavily-doped junction greatly increases the wet etch rate of the substrate. The heavily-doped junction thereby facilitates wet etching the substrate to form the trench.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of reducing trench cones in the fabrication of trenches in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to reduce the occurrence of trench cones by damaging the passive surface materials overlying the semiconductor substrate.
A yet further object of the present invention is to reduce the occurrence of trench cones by removing the damaged passive surface materials during the trench etch.
Another further object of the present invention is to provide a method to form trenches with fewer trench cones.
Another further object of the present invention is to provide a method to form shallow trench isolations with fewer trench cones.
In accordance with the objects of this invention, a new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.
REFERENCES:
patent: 4534824 (1985-08-01), Chen
patent: 5118636 (1992-06-01), Hosaka
patent: 5668044 (1997-09-01), Ohno
patent: 5780353 (1998-07-01), Omid-Zohoor
patent: 6004864 (1999-12-01), Huang et al.
Stanley Wolf Silicon Processing for the VSLI ERA vol. 2 Lattice Press p. 52.
Gerung Henry
Pradeep Yelehanka Ramachandramurthy
Zhong Qinghua
Zou Zheng
Blum David S.
Bowers Charles
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
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