Method to reduce peak current for RAS cycle sensing in DRAM...

Details Method to reduce peak current for RAS cycle sensing in DRAM... Method to reduce peak current for RAS cycle sensing in DRAM...

2001-01-16

2002-07-02

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S193000, C365S233100

Reexamination Certificate

active

06414898

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to dynamic random access memory and more particularly this invention is related to methods and circuits to select and activate memory cells of the DRAM.
2. Description of the Related Art
The structure and function of a synchronized dynamic random access memory is described in the Joint Electron Device Engineering Council (JEDEC) standard 21-C section 3.11.5 release 4 and shown schematically in
FIG. 1
a
. An array
100
of memory cells
105
is arranged in rows and columns.
FIG. 1
b
illustrates the detail of the memory array
100
. Each memory cell
105
consists of a capacitor C
105
b
and a pass transistor M
p
105
a
. The gate of each pass transistor is connected to one of the word-lines WL
0
, . . . , WLi
110
that form the rows of the array
100
of DRAM cells. The drain of the pass transistor M
p
105
a
is connected to a top plate of the capacitor C
105
b
. The bottom plate of the capacitor C
105
b
is connected commonly with all the bottom plates of the cell capacitors of the DRAM array to a reference voltage source. The source of the pass transistor M
p
105
a
is connected to one of the bit-lines BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
.
A digital data bit is stored as a quantum of electrical charge on the capacitor C
105
b
. To write or store the digital data bit to one of the memory cells
105
, the bit-line BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
containing the desired memory cell
105
is set to a voltage level indicating the logic state of a digital data bit The word-line WL
0
, . . . , WLi
110
is set to a voltage level sufficient to turn on the pass transistor M
p
105
a
and the capacitor C
105
b
is charged to the voltage level indicating the logic state of the digital data bit.
To read or fetch the digital data bit from the desired memory cell
105
, the bit-line BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
is precharged to a reference voltage Vref. The reference voltage Vref is generally one half the voltage level of the power supply voltage. The word-line WL
0
, . . . , WLi
110
containing the desired memory cell
105
is brought to the voltage level sufficient to activate the pass transistor M
p
105
a
. The charge present on the capacitor C
105
b
flows to the bit-line BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
connected to the desired memory cell
105
, if the desired memory cell
105
contains a digital data bit indicating a first logic state (
1
). The flow of charge from the capacitor C
105
b
increases the voltage level present on the bit-line BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
. However, if the capacitor C
105
b
is discharged, indicating the memory cell
105
contains a second logic state (0), charge will flow to the capacitor decreasing the voltage level on the bit-line BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
.
Returning now to
FIG. 1
a
, the row digital address word RADD
0
, . . . , RADDk
125
is an input from external circuitry identifying the row location of the array
110
containing the desired memory cell
105
. The digital address word RADD
0
, . . . , RADDk
125
is decoded by the row decoder to select the desired word-line WL
0
, . . . , WLi
110
.
The column digital address word CADD
0
, . . . , CADDj
135
is a second input from external circuitry identifying the column location of the array
100
containing the desired memory cell
105
. The column digital address word CADD
0
, . . . , CADDj
135
is decoded by the column decoder
140
to create the column select signals YAD
0
, . . . , YADm
145
. One of the column select signals YAD
0
, . . . , YADm
145
is activated to select the column containing the desired memory cell
105
.
The primary bit-lines BL
00
, . . . , BLmn
115
and the complementary bit-lines {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
are pair-wise connected to one of the sense amplifiers
150
. Each sense amplifier detects the change in voltage on one of the bit-lines BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
that results from the presence or absence of charge present on the memory cell
105
indicating the logic state of the digital data bit. The sense amplifier is a positive feedback amplifier that detects the voltage difference between the primary bit-line BL
00
, . . . , BLmn
115
and complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
and forces the primary bit-line BL
00
, . . . , BLmn
115
to the logic state of the memory cell
105
attached to it or the complementary logic state of the memory cell
105
if it is attached to the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
. Conversely, the sense amplifier forces the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
to the complement logic state of the selected memory cell
105
connected to the primary bit-line BL
00
, . . . , BLmn
115
. However, if the selected memory cell
105
is connected to the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
, the sense amplifier forces the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
to the logic state of the selected memory cell
105
.
A representative schematic of the sense amplifier
150
is shown in
FIG. 1
c
. If the primary bit-line BL
00
, . . . , BLmn
115
is at a voltage greater than the voltage level of complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
, the N-type metal oxide semiconductor transistor (NMOS) M
2
begins to conduct. This lowers the voltage present on the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
toward the level of the power supply voltage source and begins to force P-type MOS transistor (PMOS) M
3
to conduct. The primary bit-line BL
00
, . . . , BLmn
115
is then forced higher toward the voltage level of power supply voltage source VH. This positive feedback continues until the primary bit-line BL
00
, . . . , BLmn
115
has reached the voltage level of the power supply voltage source VH and the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
has reached the level of the power supply voltage source VL. Alternately, if the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
is at a voltage level larger than the voltage level on the primary bit-line BL
00
, . . . , BLmn BL
00
, . . . , BLmn, the NMOS transistor M
1
begins to conduct lowering the voltage level of the primary bit-line BL
00
, . . . , BLmn
115
toward the power supply voltage source VL. This causes the PMOS transistor M
4
to begin to conduct raising the voltage level of the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
toward the power supply voltage source VH. As described above the positive feedback will ultimately force the primary bit-line BL
00
, . . . , BLmn
115
to the voltage level of the power supply voltage source VL and the complementary bit-line {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
to the voltage level of the power supply voltage source VH.
During this sensing, amplification, and latching of the level of voltage present on the primary bit-line BL
00
, . . . , BLmn
115
and the complementary bit-line {overscore (BL
00
)}, . . . , {overscore (BLmn)}
120
, a relatively large current flows from the power supply voltage source VH to the bit-lines BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
and a relatively large current flows from the bit-lines BL
00
, . . . , BLmn
115
or {overscore (BL
00
)}, . . . {overscore (BLmn)}
120
to the power supply voltage source VL.
Returning to
FIG. 1
a
, it is apparent that when one word-line WL
0
, . . . , WLi
110
is activated, the charge level present o

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