Method to reduce noise in PLL frequency synthesis

Details Method to reduce noise in PLL frequency synthesis Method to reduce noise in PLL frequency synthesis

1993-06-08

1994-05-31

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331 27, 307516, 307528, 328134, H03L 7089

Patent

active

053172833

ABSTRACT:
A phase locked loop system including first and second counters connected respectively to first and second registers. The first register contains a number M and the second register contains a number N. The first counter is responsive to a reference signal Fref and the second counter is responsive to an output signal Fout. The first counter provides an output signal F1 responsive to M cycles of Fref and the second counter provides an output signal F2 responsive to N cycles of Fout. The F1, F2, Fref and Fout signals are connected to a phase detection circuit where the phases of Fref and Fout are compared under the control of the larger states of F1 and F2. The output signal of the phase detection circuit is connected to a voltage controlled oscillator that produces the output signal Fout proportional to the phase detection circuit output signal. The Fout signal is looped back to the second counter until the phase locked loop system settles when Fref/M equals Fout/N.

REFERENCES:
patent: 5008629 (1991-04-01), Ohba et al.

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