Method to reduce leakage of a SRAM-array

Details Method to reduce leakage of a SRAM-array Method to reduce leakage of a SRAM-array

2008-06-20

2010-10-05

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S154000, C365S226000

Reexamination Certificate

active

07808856

ABSTRACT:
A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode.

REFERENCES:
patent: 7126370 (2006-10-01), Bhattacharya
patent: 2006/0215465 (2006-09-01), Bhavnagarwala et al.
patent: 2007/0005999 (2007-01-01), Rusu et al.
patent: 2007/0040575 (2007-02-01), Afghahi et al.
J. Pille et al. Implementation of the CELL Broadband Engine In a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V, 2007 IEEE International Solid-State Circuits Conference ISSCC2007/ Session 18/ SRAM/18.1.
Nabeel Sakran et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor”, 2007 IEEE International Solid State Circuits Conference. ISSCC 2007/Session 5/MICROPROCESSORS/5.6.

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