Method to reduce defects in shallow trench isolations by...

Details Method to reduce defects in shallow trench isolations by... Method to reduce defects in shallow trench isolations by...

1999-07-19

2002-02-26

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S437000

Reexamination Certificate

active

06350662

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to a method to form shallow trench isolations in the manufacture of integrated circuits.
(2) Description of the Prior Art
As integrated circuit feature sizes continue to shrink, one of the limiting factors in this size reduction is the technique for active area isolation. Traditionally in the art, active areas have been isolated from each other through the formation of local oxidation of silicon, or LOCOS, structures. LOCOS structures provide good electrical isolation of active areas such as transistor source and drain regions. However, LOCOS structures consume substantial amounts of silicon surface area. This means that the available area for active devices such as transistors is reduced. Further, the LOCOS structure is three-dimensional and creates a non-planar surface topology that adversely affects the process yield and complexity of the processing steps that come after the LOCOS formation.
To reduce the silicon area used for isolation regions and to improve the planarity of these regions, a new technique, called shallow trench isolation, or STI, has been developed. In STI, trenches or grooves are etched into the top surface of the silicon wafer. These grooves are then filled with an isolating dielectric such as silicon oxide. This isolating dielectric is then made planar to the surface of the substrate by etching or chemical mechanical polishing (CMP). STI structures made in this way can be made substantially smaller than comparable LOCOS structures. Therefore less of the silicon surface is used for isolation and more is available for active devices. Since the STI structures are made planar, the processing problems presented by the LOCOS surface topology are solved.
Referring now to
FIG. 1
, a prior art shallow trench isolation is shown in cross-section. A semiconductor substrate
10
is shown. A shallow trench is etched into the semiconductor substrate
10
and lined with a thermally grown oxide
14
. An isolation oxide
18
is shown deposited to complete the shallow trench isolation. Overlying the semiconductor substrate
10
and the shallow trench isolation is a gate oxide
22
. A polysilicon structure
26
, such as a transistor gate, overlies the gate oxide
22
. Finally, a passivation layer
30
overlies the polysilicon structure
26
.
Two locations in the prior art structure should be especially noted. The top corners
34
of the shallow trench isolation, where the trench meets the top surface of the semiconductor substrate, and the bottom corners
38
of the trench are areas where a variety of problems can occur. The reactive ion etch (RIE) process used to etch the trench causes the formation of substrate defects, dislocations, and interface traps. The thermally grown oxide liner
14
also induces stresses into the semiconductor substrate
10
. All of these defects and conditions are especially pronounced at the corner regions
34
,
38
of the trench.
The presence of substrate defects, dislocation, and interface traps, as well as substrate stress, causes several problems. First, where these conditions occur at the top corners
34
, it is detrimental to the integrity of the gate oxide layer
22
formed overlying the trench. The voltage required to breakdown the gate oxide layer
22
is a measurement of the integrity of the gate oxide layer
22
. The presence of substrate defects near the gate oxide layer
22
reduces the measured breakdown voltage.
Second, junction breakdown voltages are also adversely effected by the shallow trench isolation defects, both at the top corners
34
and at the bottom corners
38
. As the breakdown voltage decreases, the integrated circuit device becomes unreliable or the operating voltage range must be limited.
Finally, in the manufacture of dynamic random access memory (DRAM) and static random access memory (SRAM) devices, shallow trench isolation defects, such as described above, cause reduced data retention times and increased power dissipation. Yield is reduced as integrated circuit devices cannot meet product specifications.
Several prior art approaches attempt to improve shallow trench isolation technology. U.S. Pat. No. 5,433,794 to Fazan et al teaches a process to create a shallow trench isolation with a dome-shaped oxide plug to reduce leakage current. U.S. Pat. No. 4,472,873 to Ko discloses a process where a nitrogen anneal is performed to reduce stacking faults in a silicon substrate due to ion implantation. U.S. Pat. No. 5,447,884 to Fahey et al discloses the use of a nitride liner layer for a shallow trench isolation and a pyrogenic oxide anneal at 800 degrees C. to drive out impurities and to reduce structural stress. U.S. Pat. No. 5,395,790 to Lur teaches a process to form a stress-free isolation layer. Stress-relief trenches are etched through the isolation oxide plug. An anneal is performed and the stress reduction trenches are refilled. U.S. Pat. No. 5,643,823 to Ho et al discloses a process to form a crystalline silicon nitride liner layer for a shallow trench isolation. A pure nitrogen or ammonia anneal of the silicon nitride layer is performed to crystallize the silicon nitride. U.S. Pat. No. 5,858,858 to Park et al teaches a process to form shallow trench isolations where a nitrogen anneal is performed after the trench oxide is deposited to fill the trench.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating integrated circuits with shallow trench isolations.
A further object of the present invention is to provide a method of fabricating shallow trench isolations using a nitrogen anneal after oxide liner growth to reduce or eliminate substrate defects, dislocations, interface traps, and structural stress.
Another further object of the present invention is to provide a method of fabricating shallow trench isolations using a nitrogen anneal after oxide liner growth to reduce the likelihood of shallow trench isolation induced low gate oxide breakdown voltages and high junction leakage currents.
In accordance with the objects of this invention, a new method of fabricating an integrated circuit with shallow trench isolations using a nitrogen anneal after liner oxide growth is achieved. A semiconductor substrate layer is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A photoresist layer is deposited overlying the silicon nitride layer and is developed to expose the silicon nitride layer in areas where shallow trench isolations are planned. The silicon nitride layer, the pad oxide layer, and the semiconductor substrate are etched where the silicon nitride layer is not protected by a photoresist mask and where the etching forms shallow trenches. The photoresist layer is stripped away. A liner oxide layer is grown overlying the semiconductor substrate on the interior surfaces of the shallow trenches. An anneal is performed on the semiconductor substrate and the liner oxide layer to reduce semiconductor substrate defects, dislocations, interface traps, and stress. An isolation oxide layer is deposited overlying the silicon nitride layer and the liner oxide layer to completely fill the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The isolation oxide layer and the pad oxide layer are etched down to the top surface of the semiconductor substrate to thereby form the shallow trench isolations, and the fabrication of the integrated circuit device is completed.


REFERENCES:
patent: 4472873 (1984-09-01), Ko
patent: 5395790 (1995-03-01), Lur
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5643823 (1997-07-01), Ho et al.
patent: 5858858 (1999-01-01), Park et al.
patent: 5981355 (1999-11-01), Lee
patent: 6083808 (2000-07-01), Shin et al.

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