Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1998-10-01
2001-04-03
Chaudhari, Chandra (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Resistor
Reexamination Certificate
active
06211031
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of forming gates, resistors, and capacitors in the fabrication of integrated circuits, and more particularly, to a method of forming gates, resistors, and capacitors having different polysilicon resistances in the manufacture of integrated circuits.
(2) Description of the Prior Art
In order to form different polysilicon resistances for the gate, resistor, and capacitor plate in an integrated circuit, the area and length of the polysilicon must be modified to meet the different criteria. This is a complex process that will increase the cost of manufacturing. Related process issues such as lateral diffusion are also a concern.
Co-pending U.S. patent application Ser. No. 09/073,948 (TSMC-97-515) to Chen et al, filed on May 7, 1998, teaches patterning a polysilicon layer to form different thicknesses of polysilicon and then doping the polysilicon to form resistors having different resistances. Co-pending U.S. patent application Ser. No. 09/073,950 (TSMC-97-508) to Shen et al, filed on May 7, 1998, teaches forming different thicknesses of an oxide layer over a polysilicon layer and then doping the polysilicon through the different oxide thicknesses to form resistors having different resistances. U.S. Pat. No. 5,554,554 to Bastani et al teaches forming high and low resistance poly loads by a selective ion implantation process. U.S. Pat. No. 5,705,418 to Liu shows a method of forming high-resistance load resistors by using a LOCOS process to reduce the thickness of portions of a polysilicon layer. U.S. Pat. No. 5,514,617 to Liu and U.S. Pat. No. 5,554,873 to Erdeljac et al teach selective a doping to form variable resistance polysilicon. U.S. Pat. No. 4,643,777 to Maeda shows selective ion implantation to form low resistance polysilicon regions. U.S. Pat. No. 5,662,884 to Liu discloses a high resistance poly load resistor. U.S. Pat. No. 5,474,948 to Yamazaki discloses a poly load resistor.
SUMMARY OF THE INVENTION
Accordingly, it is a principal object of the present invention to provide an effective and very manufacturable method of forming a gate, resistor, and capacitor plate having differing polysilicon resistances.
A further object of the invention is to provide a method for forming polysilicon resistors having differing resistances.
A still further object is to provide a method for forming polysilicon resistors having differing resistances using a dual polysilicon process.
Another object of the invention is to control polysilicon resistance using different polysilicon thicknesses.
Yet another object is to provide a method for producing different polysilicon resistances using one-time doping.
Yet another object of the invention is to provide a method for eliminating lateral diffusion of dopant by doping after patterning the polysilicon.
In accordance with the objects of this invention a new method of forming polysilicon resistors having differing resistances using a dual polysilicon process is achieved. A first polysilicon layer is deposited over a dielectric layer on a semiconductor substrate. The first polysilicon layer is etched away where it is not covered by a mask. Thereafter, a second polysilicon layer is deposited overlying the first polysilicon layer and the dielectric layer. The first and second polysilicon layers are patterned to form a first polysilicon structure comprising the first and second polysilicon layers over the dielectric layer and a second polysilicon structure comprising the second polysilicon layer overlying the dielectric layer. The first and second polysilicon structures are doped to form the first polysilicon structure having a first resistance and the second polysilicon structure having a second resistance wherein the first resistance is lower than the second resistance.
REFERENCES:
patent: 4643777 (1987-02-01), Maeda
patent: 5474948 (1995-12-01), Yamazaki
patent: 5514617 (1996-05-01), Liu
patent: 5554554 (1996-09-01), Bastani et al.
patent: 5554873 (1996-09-01), Erdeljac et al.
patent: 5622884 (1997-04-01), Liu
patent: 5705418 (1998-01-01), Liu
patent: 6143474 (2000-11-01), Shen et al.
Chen Sen-Fu
Lin Dah-Chih
Shen Chin-Heng
Ackerman Stephen B.
Chaudhari Chandra
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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