Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-06-01
2000-06-06
Smith, Matthew
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438425, 438702, H01L 2176
Patent
active
060717947
ABSTRACT:
A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.
REFERENCES:
patent: 4900692 (1990-02-01), Robinson
patent: 4994406 (1991-02-01), Vasquez et al.
patent: 5098856 (1992-03-01), Beyer et al.
patent: 5183775 (1993-02-01), Levy
patent: 5298790 (1994-03-01), Harmon et al.
patent: 5650639 (1997-07-01), Schrantz et al.
patent: 5783476 (1998-07-01), Arnold
patent: 5911109 (1999-06-01), Razouk et al.
Kao Ming-Kuan
Li Jui-Ping
Lin Ping-Wei
Chou Chien-Wei (Chris)
Mosel Vitelic Inc.
Rocchegiani Renzo
Smith Matthew
LandOfFree
Method to prevent the formation of a thinner portion of insulati does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to prevent the formation of a thinner portion of insulati, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to prevent the formation of a thinner portion of insulati will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2212860