Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-06-30
2003-07-29
Rose, Robert A. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S057000
Reexamination Certificate
active
06599173
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to chemical mechanical planarization of integrated circuit surfaces, and in particular, to a composition and method of removing metal layers when forming interconnect structures. The composition and method of the present invention provides enhanced removal of residual metal and liner material from the interconnect structure while reducing scratching of the underlying dielectric layers.
2. Description of Related Art
Integrated circuits are chemically and physically integrated into a semiconductor substrate by patterning layers on the substrate. These layers can be conductive, for conductor and resistor fabrication. A thousand or more devices can be formed simultaneously on the surface of a single wafer of semiconductor material. It is essential for high device yields to start with a flat semiconductor wafer. If the process steps of device fabrication are performed on a wafer surface that is not planar, various problems can occur which may result in premature device failure. Since any irregularities on the wafer surface may be magnified as subsequent layers are formed thereon, it is desirable for the layers and the substrate to be as planar as possible.
Semiconductor fabrication generally comprises providing tungsten or copper wiring or metallization in discrete layers of dielectric oxide film. Typical oxides include silicon dioxide, phosphosilicate glass, borophosphosilicate glass, and other like materials. Thereafter, the oxide is etched to form vias or trenches. A liner material is blanket deposited as a thin layer into the trenches to provide good adhesion for the subsequent metal fill and acts as a diffusion barrier. The liner material generally comprise titanium, titanium nitride, tantalum, tantalum nitride and mixtures thereof. The subsequent metallization is conformally deposited comprising tungsten or copper. Thus, the filled trenches form lines and the filled holes form vias or interconnects. The process is typically completed when the liner material and metallization are removed using chemical mechanical planarization (CMP) down to the surface of the dielectric film.
Typically, during CMP, the semiconductor wafer is held against a rotating polishing pad surface under a controlled downward pressure. A slurry containing an abrasive and either a basic or acidic solution is provided to remove the liner material and copper or tungsten metallization. Problems arising from this methodology involve sufficient removal of the metallization and liner material which may create isolated metal islands which can lead to shorts in the semiconductor device.
Oftentimes, the metallization, particularly with the tungsten, is removed by over-polishing the surface of the wafer to ensure that there are no metal residues remaining. Any metal residues which remain are not removed in subsequent steps and may lead to shorts in the device. However, the over-polishing tends to cause “dishing,” erosion of the metallization within the via or interconnect, which leads to metal open defects. Furthermore, the liner material has proven problematic in its removal, tending to remain behind in localized topography caused by prior level “dishing” and in scratches of the wafer surface.
Attempts to remove the liner material also result in surface defects of the underlying dielectric. It is common to continue the CMP until substantially all of the liner material has been removed from the underlying dielectric and follow up with another step for touching up the dielectric surface. The follow up hopes to remove any residual liner material and replanarize the dielectric surface to correct any defects caused by the CMP. However, care must be taken such that the dielectric is not eroded beyond acceptable process parameters particularly in areas of high density metallization.
U.S. Pat. No. 5,676,587 to Landers and assigned to the assignee of the present invention discloses a silica based slurry used to remove liner material comprising titanium/titanium nitride or tantalum/tantalum nitride. However, the slurry is ineffective in removing any tungsten residues which causes severe metal shorting in the resultant device. Therefore, the metallization must be over-polished in order to ensure thorough removal of the metallization and the liner material followed by recessing the dielectric layer. The silica based slurry used to remove the liner material does so efficiently without removing much tungsten or dielectric material. However, any tungsten residue that remains on the wafer service will create isolated metal islands leading to shorts and premature device failure.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a CMP method which effectively removes metal residues and liner material, preferably in a single step.
It is another object of the present invention to provide a CMP method which effectively removes metal residues and liner material from a surface of the underlying dielectric without the need for over-polishing of the metallization.
A further object of the invention is to provide a CMP method which effectively removes metal residues and liner material which does away with the need for surface touch up of the dielectric.
It is yet another object of the present invention to provide an enhanced method of forming an interconnect structure which provides a substantially planar upper surface of the underlying dielectric layer.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of chemical mechanical polishing a semiconductor wafer surface having excess metal used in forming one or more metal interconnects comprising the steps of: polishing the wafer surface with a first oxidizer to remove a substantial portion of the excess metal while leaving a metal residue; and removing the metal residue with a second oxidizer having a higher affinity for the metal residue than the first oxidizer. Preferably, the step of polishing the wafer surface comprises polishing the wafer surface with an amount of ferric nitrate less than about 5 wt. % of a total amount of a polishing slurry. Additionally, the first oxidizer further includes an abrasive comprising alumina.
Preferably, the step of removing the metal residue with a second oxidizer comprises removing the metal residue and a liner material used in forming the interconnects. Most preferably, the step of removing the metal residue with a second oxidizer comprises removing the metal residue with postassium iodate wherein the slurry has a pH of about 7 to 9.
In a second aspect, the present invention is directed to a method of polishing a semiconductor wafer comprising the steps of: providing a semiconductor wafer having an interconnect structure wherein a top surface of the wafer has a blanket layer of liner material and a blanket layer of excess metal disposed thereover; chemical mechanical polishing the wafer to remove the blanket layer of excess metal with a first slurry comprising a metal oxidizing agent while leaving a metal residue; chemical mechanical polishing the wafer to remove the metal residue with a second slurry comprising another oxidizing agent having an affinity for the excess metal and the linear material; and prevent scratching of a dielectric material beneath the liner material.
Preferably, the step of providing a semiconductor wafer comprises providing a semiconductor wafer having an interconnect structure wherein a top surface of the wafer has a blanket layer of liner material comprising titanium nitride and a blanket layer of excess metal comprising tungsten disposed thereover, an interconnect structure wherein a top surface of the wafer has a blanket layer of liner material comprising tantalum nitride and a blanket layer of
Cruz Jose L.
Huynh Cuc K.
Krywanczyk Timothy C.
Sturtevant Douglas K.
DeLio & Peterson LLC
Reynolds Kelly M.
Rose Robert A.
Walsh Robert A.
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