Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-06-24
2000-01-25
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438437, 438435, 438692, 438424, H01L 2176
Patent
active
060178035
ABSTRACT:
A method is described for filling trenches in a substrate for shallow trench isolation or for a metal damascene structure which will prevent dishing when the substrate is planarized using chemical mechanical polishing. Trenches are formed in the substrate. A layer of first material is formed on the substrate, sidewalls of the trench, and bottom of the trench. A layer of second material is then formed on the layer of first material. The substrate is then planarized using a chemical mechanical polishing. The first material, second material, and parameters of the chemical mechanical polishing are chosen so that the removal rate of the first material is greater than the removal rate of the second material. The chemical mechanical polishing then results in a planar substrate with no dishing.
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Chartered Semiconductor Manufacturing Ltd.
Dang Trung
Pike Rosemary L. S.
Prescott Larry J.
Saile George O.
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