Method to prevent antifuse Si damage using sidewall spacers

Details Method to prevent antifuse Si damage using sidewall spacers Method to prevent antifuse Si damage using sidewall spacers

2002-01-04

2004-08-10

Zarneke, David A. (Department: 2829)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

C438S600000

Reexamination Certificate

active

06773967

ABSTRACT:

BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to the fabrication of antifuse-based, programmable interconnect links, for field programmable gate arrays, (FPGA) for semiconductor devices and more particularly method for forming sidewall spacers on antifuse to prevent damage during subsequent metal etching.
2) Description of the Prior Art
Field-programmable gate arrays, (FPGA), have been designed to contain the needed row of arrays, as well as additional rows of spare arrays accessed if needed to replace ineffective counterparts, or to modify a specific design. Recent FPGA designs, feature one-time fusible link structures as possible programmable low resistance interconnect links, if accessed. These additional or spare arrays, or one-time fusible link structures, are sometimes comprised of an antifuse based programmable interconnect structure. The structure consists of an antifuse layer, usually a thin dielectric layer, placed between electrodes or conductive materials. When needed this antifuse material can be ruptured, or converted to a lower resistance layer, via a high voltage electrical pulse, resulting in creation of the replacement array structure.
The antifuse layer, used with the one-time fusible link structure, can be a dielectric layer, such as silicon oxide or silicon nitride. However to perform as an antifuse layer, the dielectric layer has to be thin, to allow reasonable programmable voltages to be successfully used. Thus small increases in the thickness of the thin antifuse dielectric layer, due to uniformity's in the dielectric layer deposition procedure, may result in inadequate programmed links. U.S. Pat. No. 5,807,786 (Chang), (assigned to the same assignee as the invention) describes a simpler process for forming one-time fusible link structures, using an amorphous silicon layer as the antifuse layer. However to avoid contamination, and additional oxide growth, on the amorphous silicon layer, during patterning procedures, a thin conductive barrier layer is used to overlie, and protect, the amorphous silicon antifuse layer, during specific fabrication sequences.
A problem the inventors have discovered is that the sidewalls of amorphous Silicon anti-fuses are damaged (and etched laterally) during the etching of the second electrode (the overlaying metal layer). This invention addresses the problem of lateral etching of the Amorphous Si antifuse.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently mote relevant technical developments in the patent literature can be gleaned by considering the following patents. U.S. Pat. No. 5,508,220 (Eltoukhy et al.) shows a method to form antifuses. U.S. Pat. No. 5,763,299 (McCollum et al.) shows a method to reduce leakage for antifuses. McCollum uses silicon nitride (SiN) layers and a barrier layer over the antifuse. U.S. Pat. No. 5,807,786 (Chang) shows a barrier layer to protect an antifuse. However, none of these patents effectively solves the problem of lateral etching of the Amorphous antifuse during the etching of the overlying metal layer.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a structure offering a one-time fusible link, for field programmable gate array designs.
It is another object of this invention to use an antifuse based interconnect, featuring an amorphous silicon, antifuse layer, for the one-time fusible link structure.
It is another object of this invention to use an antifuse based interconnect, featuring an amorphous silicon antifuse layer, for the one-time fusible link structure that has a silicon nitride anti-fuse sidewall spacer that protects the amorphous Si antifuse form antifuse from etchants and prevent lateral etching of the amorphous Si antifuse.
It is yet another object of this invention to form the amorphous Si antifuse having a SiN sidewall spacer that protects the amorphous Si antifuse form antifuse from etchants and protects the sidewalls of the amorphous silicon layer from subsequent processing procedures.
To accomplish the above objectives, the present invention provides a method of manufacturing an antifuse based interconnect structure, to be used for a one-time fusible link. A semiconductor substrate, comprised of overlying metal interconnect patterns, contacting conductive regions in the semiconductor substrate, is provided. A first metal interconnect structure, to be used as the lower electrode of the antifuse based interconnect structure, is formed, contacting conductive regions in the semiconductor substrate. An interlevel dielectric layer is deposited, preferably followed by a chemical mechanical polishing procedure, used for planarization purposes. A via hole opening is created in the interlevel dielectric layer, exposing the top surface of the first metal interconnect structure. A metal layer is deposited filling the via hole forming a metal plug. An amorphous silicon antifuse layer is next deposited. Patterning, using photolithographic and dry etching procedures, is used to form an amorphous Si antifuse, overlying the metal plug.
In a key step, protective antifuse sidewalls spacers
20
are formed on the antifuse
7
sidewalls. The protective spacers are formed of an etch resistance material and preferably of silicon nitride. A second metal layer is deposited thereover. A photoresist layer is formed over the second metal layer. The second metal layer is etched preferably using an etch chemistry, such as Cl
2
, or BCl
3
, that also could etch the amorphous Si antifuse if the invention's spacers where not protecting the antifuse sidewalls.
The metal layer is patterned to form a second interconnect structure, to be used as the upper electrode of the antifuse based interconnect structure, overlying the composite antifuse layer. The invention's protective spacers protect the Silicon amorphous silicon containing antifuse from etch damage in the upper electrode etch process.
The invention solves the following problems:
1. Prevents the amorphous Si antifuse sidewall from being damaged at the subsequent metal (upper electrode) etch.
2. Prevents the amorphous Si antifuse sidewalls from being damaged by stripper in the polymer strip step after metal etch.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.


REFERENCES:
patent: 5250464 (1993-10-01), Wong et al.
patent: 5308795 (1994-05-01), Hawley et al.
patent: 5508220 (1996-04-01), Eltoukhy et al.
patent: 5763299 (1998-06-01), McCollum et al.
patent: 5804500 (1998-09-01), Hawley et al.
patent: 5807786 (1998-09-01), Chang
patent: 6107165 (2000-08-01), Jain et al.
patent: 6124193 (2000-09-01), Hawley et al.
patent: 6265257 (2001-07-01), Hsu et al.

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