Method to manufacture field emission array with self-aligned foc

Details Method to manufacture field emission array with self-aligned foc Method to manufacture field emission array with self-aligned foc

1999-08-12

2000-04-04

Ramsey, Kenneth J.

Electric lamp or space discharge component or device manufacturi

Process

With assembly or disassembly

445 50, H01J 902

Patent

active

060454261

ABSTRACT:
A process for forming self-aligned focus electrodes in an FED display is described. The process begins by forming cathode columns and gate lines in the normal way, care being taken to ensure that at the intersections between these two sets of lines (where the emitter cavities will reside) the material comprising the cathode columns is transparent to light that will expose photoresist. To this end, ITO is used with an overlay of amorphous silicon in areas well away from the intersections. With cathode and gate lines in place, a second dielectric layer is deposited and material for the focus electrodes is laid down, said material also being transparent as well as conductive, a preferred choice being ITO. Photoresist is then laid down over the upper ITO layer but, in a departure from normal practice, it is exposed to light coming from the bottom of the substrate. Thus, the gate lines act as shadow masks for exposing the photoresist on the top ITO layer, resulting in perfect alignment of the focus lines with the gate lines, cathode columns, and emitter cavities (after etching). The final step is the formation of the microtips inside the emitter cavities in the usual way.

REFERENCES:
patent: 5186670 (1993-02-01), Doan et al.
patent: 5649847 (1997-07-01), Haven
patent: 5710483 (1998-01-01), Peng
patent: 5757138 (1998-05-01), Tsai
patent: 5920151 (1999-07-01), Barton et al.

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