Method to isolate device layer edges through mechanical spacing

Details Method to isolate device layer edges through mechanical spacing Method to isolate device layer edges through mechanical spacing

2002-08-29

2004-05-18

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S003000, C438S238000, C438S381000, C257S295000, C257S659000

Reexamination Certificate

active

06737283

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to magnetic random access memory (MRAM) cells and a method for fabricating the same.
BACKGROUND OF THE INVENTION
Magnetic random access memories (MRAMs) employ a plurality of memory cells each formed as a stack of spaced thin magnetic multilayer films. When in use, an MRAM cell stores information as a digital bit based on the relative magnetic orientations of the magnetic layers in the stack. Each MRAM cell has two stable magnetic film orientations, one which produces a high resistance across the cell representing) e.g., a logic state
0
, and another which produces a lower resistance across the cell representing, e.g., a logic state
1
, or vice versa.
A typical MRAM structure includes an array having a number of bit or digit (column) lines intersected by a number of word (row) lines. An MRAM cell is formed between a digit line and a row line at each intersection.
FIG. 1
shows an exemplary conventional MRAM structure including a plurality of MRAM cells
22
formed at the intersections of a number of bit or digit lines
18
and word line
23
. The digit lines
18
are typically formed of copper (Cu) in an insulating layer
16
. Both the digit lines
18
and the insulating layer are formed over underlayers
14
of an integrated circuit (IC) substrate
10
, wherein, the underlayers
14
may include, for example, portions of integrated circuitry, such as CMOS circuitry.
For each row of MRAM cells in the array, all of the MRAM cells in the row are coupled to a word line that intersects each of the bit lines. In the example shown in
FIG. 1
, the three MRAM cells
22
seen in the drawing are coupled to word line
23
which intersects the corresponding bit lines
18
. While word line
23
and bit lines
18
are illustrated as seen in
FIG. 1
, the positions and functions of word line
23
and bit lines
18
may be interchanged.
The basic memory MRAM cell has a pinned magnetic layer having a fixed magnetic orientation, a free (sense) magnetic element having an orientation which is changeable between two orientations, and a nonmagnetic layer between them. In magnetic tunnel junction (MTJ) MRAM devices, the nonmagnetic layer is typically known as a tunnel junction layer. The orientation of the free (sense) element is set in accordance with the direction of an applied magnetic field for writing logical data to be stored by the cell.
Each of the two orientations of the sense element in the MRAM cells is assigned a bit value of either “0” or “1.” Data is stored in an MRAM cell by applying a magnetic field produced by transmitting signals in the appropriate directions through the respective digit line
18
and word line
23
which intersect at the desired cell into which data is to be written. The stored data is retained in the MRAM cell until it is overwritten by another Write operation on the same cell.
Data stored in the MRAM cells is read by measuring the resistance through each cell in a vertical direction extending through the pinned magnetic element, the tunnel junction layer and the sense magnetic element. The resistance of an MRAM cell is measured by transmitting a current through the tunnel junction layer from one of the magnetic elements to the other. A reference current level is set to a value in between that obtained from an MRAM cell in an antiparallel orientation and that obtained from an MRAM cell in a parallel orientation. When a read current from a selected MRAM cell is greater than the reference current, the value stored in the MRAM cell is interpreted to be a “1,” whereas when the read current is less than the reference current, the stored value is interpreted to be a “0.”
FIG. 2
illustrates a side sectional view of the MRAM structure seen in
FIG. 1
, wherein a pinned magnetic element
20
of a respective MRAM cell
22
is provided over each digit line
18
. A tunnel junction layer
25
is formed over the pinned magnetic element
20
, and a free (sense) magnetic element
21
is provided over the tunnel junction layer. A word line
23
is provided over the sense magnetic element
21
of all the MRAM cells
22
in a row. Typically, pinned magnetic element
20
and sense magnetic element
21
are each formed of ferromagnetic materials, while tunnel junction layer
25
is made of a nonmagnetic, electrically conductive material such as, for example, Al
2
O
3
. Together, each stack composed of the pinned magnetic element
20
, the tunnel junction layer
25
and the sense magnetic element
21
forms an MRAM cell
22
.
Additionally, a bottom conductive barrier layer
24
composed of, for example, tantalum (Ta), is formed at the base of the pinned magnetic element
20
to improve adhesion of the pinned layer to the material forming the respective bit line
18
. Similarly, the barrier layer
24
also lines the trenches in insulating layer
16
in which the bit lines
18
are formed.
A schematic view of the layers of a typical MRAM stack is shown in FIG.
3
and may include a first barrier layer
24
a
composed of Ta to enhance bonding between the adjacent layers; a first conductive layer
19
made of copper (Cu) (for forming the bit line
18
); a second Ta barrier layer
24
b
; a pinned magnetic element
20
formed of a magnetic seed layer
20
a
made of Nickel/Iron (NiFe), an antiferromagnetic layer
20
b
made of Iridium/Manganese (Ir/Mn), and an NiFe magnetic layer
20
c
having its magnetic orientation pinned by the antiferromagnetic layer
20
b
; a nonmagnetic, electrically conductive tunnel junction layer
25
made of Aluminum Oxide (Al
2
O
3
); a sense magnetic element formed of an NiFe magnetic layer
21
; a third Ta barrier layer
27
; and a second conductive layer
28
(for forming the word line
23
).
Fabrication of such stacks forming the complete MRAM cells requires deposition of the thin materials layer by layer, according to a predefined order, in conjunction with an etching process to define the individual cells. During a dry etching step typically performed to define the cells
22
such as ion milling, for example, the conductive layers may sputter back onto the sidewalls of the stacks, forming a side conductive layer
26
and creating an undesirable electrical short between the pinned magnetic element
20
and sense magnetic element
21
. Thus, during a read operation, the current may flow through the side conductive layer
26
rather than flow through the tunnel junction layer
25
, causing improper resistance sensing. Hence, what is needed is a method of fabricating an MRAM cell which will not create a short as described above.
BRIEF SUMMARY OF THE INVENTION
The present invention provides an MRAM cell and a method of forming the same which minimizes the occurrence of electrical shorts during fabrication. According to the present invention, a first conductor is provided in a trench in an insulating layer, and then an upper surface of the insulating layer and the first conductor are planarized. Next, as the layers forming the stacks of the MRAM cells are deposited on the planarized insulating layer and first conductor, the critical layers are physically separated from adjacent layers at regions surrounding an interior region of the stacked layers. The stacked layers at the interior region form an MRAM cell, while the separated edges prevent a conductive layer from being formed along the sidewalls of the MRAM cell due to sputtering during an etching process performed to define the cell.


REFERENCES:
patent: 4357369 (1982-11-01), Kilichowski et al.
patent: 4396704 (1983-08-01), Taylor
patent: 4426247 (1984-01-01), Tamamura et al.
patent: 4433044 (1984-02-01), Meyer et al.
patent: 4523372 (1985-06-01), Balda et al.
patent: 4552833 (1985-11-01), Ito et al.
patent: 5079131 (1992-01-01), Thackeray et al.
patent: 5487967 (1996-01-01), Hutton et al.
patent: 5940319 (1999-08-01), Durlam et al.
patent: 6024885 (2000-02-01), Pendharkar et al.
patent: 6204524 (2001-03-01), Rhodes
patent: 6348365 (2002-02-01), Moore et al.
patent: 6358756 (2002-03-01), Sandhu et al.
patent: 6555858 (2003-04-01), Jones et al.

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