Method to integrate HBTs and FETs

Details Method to integrate HBTs and FETs Method to integrate HBTs and FETs

1991-03-15

1991-12-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437 59, 437126, 437133, 148DIG9, 148DIG72, H01L 2118

Patent

active

050772317

ABSTRACT:
This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

REFERENCES:
patent: 4821090 (1989-04-01), Yokoyama
patent: 4830980 (1989-05-01), Hsieh
patent: 4929570 (1990-05-01), Howell
patent: 5012318 (1991-04-01), Honjo
Itakura et al., "A GaAs Bi-FET Technology For Large Scale Integration", IEDM, 1989, pp. 389-392.
K. Itakura et al.; A GaAs Bi-FET Technology for Large Scale Integration; IEEE 1989; pp. 15.2.1-15.2.4.

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