Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-05-12
2000-11-28
Meier, Stephen D.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438257, 438294, 438296, 438211, H01L 2176
Patent
active
061534943
ABSTRACT:
A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.
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Anonymous, "Flash Memory Cell using the RSTI (Raised Shallow Trench Isolation)", May 1998, Research Disclosure 409142, pp. 651-652.
Chen Jong
Hsieh Chia-Ta
Jung Lin Chrong
Kuo Di-Son
Lin Yai-Fen
Ackerman Stephen B.
Davis Jamie L.
Meier Stephen D.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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