Method to incorporate non-volatile memory and logic components i

Details Method to incorporate non-volatile memory and logic components i Method to incorporate non-volatile memory and logic components i

1997-01-17

1998-03-03

Trinh, Michael

Fishing, trapping, and vermin destroying

437 43, 437 47, 437 52, H01L 218247

Patent

active

057233551

ABSTRACT:
A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

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