Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2004-12-02
2010-02-02
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331SDIG002, C327S157000, C713S323000
Reexamination Certificate
active
07656237
ABSTRACT:
An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.
REFERENCES:
patent: 5594735 (1997-01-01), Jokura
patent: 6694441 (2004-02-01), Sethia
patent: 6763060 (2004-07-01), Knapp
patent: 6990165 (2006-01-01), Boerstler et al.
patent: 7036032 (2006-04-01), Mizuyabu et al.
Riley Mack Wayne
Stasiak Daniel Lawrence
Wang Michael Fan
Weitzel Stephen Douglas
Goodley James E
International Business Machines - Corporation
Pascal Robert
Talpis Matthew B.
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