Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-06-14
2000-10-31
Bowers, Charles
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438221, 438296, 438359, H01L 2176
Patent
active
061402060
ABSTRACT:
A method of forming a shallow trench isolation trenches in a silicon substrate of an integrated circuit device is achieved. A silicon substrate is provided. A buffer layer is deposited overlying the silicon substrate. An etching endpoint layer is deposited overlying the buffer layer. A silicon layer is deposited layer overlying the etching endpoint layer. A photoresist layer is coated overlying the silicon layer. The photoresist layer is developed wherein the photoresist layer is removed where the trenches are planned. The silicon layer, the etching endpoint layer, and the buffer layer are etched through to expose the top surface of the silicon substrate. The silicon layer and the silicon substrate layer are etched until the top surface of the etching endpoint layer is exposed, and the trenches are thereby formed. The integrated circuit device is completed.
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Li Jian Xun
Zhong Qing Hua
Zhou Mei Sheng
Blum David S
Bowers Charles
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
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