Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-09-03
2001-03-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000
Reexamination Certificate
active
06207534
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the formation of narrow and wide shallow trench isolations with different depths to eliminate isolation oxide dishing problems.
(2) Description of the Prior Art
The use of shallow trench isolation (STI) for the formation of integrated circuit isolations has grown in the art due to the reduced surface area and improved topology of STI when compared to traditional local oxidation of silicon (LOCOS) schemes. One problem that is encountered in the use of STI is oxide dishing. Oxide dishing occurs, in part, due to pad deformation in the chemical mechanical polish (CMP) process used to planarize the STI structures. It is called dishing because the STI isolation oxide takes on the shape of a dish as the oxide in the trench is thinned by the CMP process. Dishing is especially pronounced on large or wide STI structures because the isolation oxide over these trenches is typically thinner than the oxide deposited over narrow trenches due to topological effects. Narrower STI structures demonstrate little or no dishing.
Referring to
FIG. 1
, a cross-section of a partially completed prior art integrated circuit is shown. A silicon substrate
10
is shown. A pad oxide layer
19
overlies the silicon substrate
10
. A silicon nitride layer
20
overlies the pad oxide layer
19
as a polishing stop. Two narrow trenches
14
and one wide trench
18
have been etched into through the pad oxide layer
19
and the silicon nitride layer
20
and into the surface of the silicon substrate
10
. The trenches have a common depth of LI because all were formed by the same reactive ion etch (RIE) process.
Referring to
FIG. 2
, an isolation oxide layer
22
has been deposited overlying the silicon nitride layer
20
and filling the trenches. Note how the topology of the trenches affects the topology of the isolation oxide layer
22
. Where the isolation oxide layer
22
overlies the narrow trenches
14
, it is relatively thick. Conversely, the isolation oxide layer
22
is relatively thin overlying the wide trench
18
.
Referring to
FIG. 3
, the result of the chemical mechanical polish (CMP) is shown. The isolation oxide layer
22
has been polished down to the top surface of the silicon nitride layer
20
to complete the shallow trench isolations. Following the polish, however, significant dishing
24
is seen over the wide trench
18
. This dishing
24
can cause increased current leakage and decreased gate oxide voltage breakdown. These problems at the active area interface reduce device yield.
Several prior art approaches disclose methods to create trenches having different depths into the substrate. U.S. Pat. No. 5,776,817 to Liang teaches a method to form trenches of different depths comprising: forming sacrificial refractory metal layers of different thickness, annealing the metal layers to create metal silicide layers of different depths into the underlying silicon substrate, and then removing the refractory metal and silicide layers to reveal trenches of different depths. U.S. Pat. No. 5,814,547 to Chang discloses a process to etch trenches using a microloading effect to cause the trenches to be etched to different depths. U.S. Pat. No. 5,851,928 to Cripe et al discloses a process to etch features of different depths in a single wet isotropic etching step by using a mask layer with different sized openings. U.S. Pat. No. 5,157,003 to Tsuji et al teaches a process to etch trenches of different depths. Selective exposure of phenol resin positive photoresist is used to define etching areas. Two etching steps are performed to form shallow trenches of two different depths.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating shallow trench isolations in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate shallow trench isolations in which isolation oxide dishing is eliminated.
A yet further object of the present invention is to eliminate isolation oxide dishing in shallow trench isolations by forming wide trenches of lesser depth than narrow trenches.
Another object of the present invention is to provide a method to fabricate shallow trenches of different depths in the same etching step.
In accordance with the objects of this invention, a new method of fabricating shallow trench isolations has been achieved. A silicon substrate is provided. A pad oxide layer is formed overlying the silicon substrate. A polishing stop layer is formed overlying the pad oxide layer. An oxide layer is deposited overlying the polishing stop layer. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the top surface of the silicon substrate to form openings for planned first trenches. A polysilicon layer is deposited overlying the oxide layer and filling the openings for the planned first trenches. The polysilicon layer is polished down to the top surface of the oxide layer such that the polysilicon layer remains only in the openings of the planned first trenches. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the top surface of the silicon substrate to form openings for planned second trenches. The polysilicon layer and the silicon substrate are etched simulataneously to complete the first trenches and the second trenches where the second trenches are etched deeper than the first trenches and where the oxide layer acts as an etching mask. An isolation oxide layer is deposited overlying the oxide layer and filling the first trenches and the second trenches. The isolation oxide layer and the oxide layer are polished down to the top surface of the polishing stop layer to complete the shallow trench isolations, and the integrated circuit device is completed.
REFERENCES:
patent: 4211582 (1980-07-01), Horng et al.
patent: 5157003 (1992-10-01), Tsuji et al.
patent: 5473186 (1995-12-01), Morita
patent: 5776817 (1998-07-01), Liang
patent: 5814547 (1998-09-01), Chang
patent: 5851928 (1998-12-01), Cripe et al.
patent: 5893744 (1999-04-01), Wang
patent: 6018186 (2000-01-01), HSU
Cha Cher Liang
Chan Lap
Lee Teck Koon
Chartered Semiconductor Manufacturing Ltd.
Niebling John F.
Pike Rosemary L.S.
Pompey Ron
Saile George O.
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