Method to form metal-to-metal antifuse for field programmable ga

Details Method to form metal-to-metal antifuse for field programmable ga Method to form metal-to-metal antifuse for field programmable ga

1997-08-05

1999-08-10

Niebling, John F.

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

438600, 257 50, 257530, H01L 2182

Patent

active

059372818

ABSTRACT:
A method of fabricating an antifuse structure for field programmable gate array (FPGA) applications is described. First, a field oxide layer for isolation is grown on the semiconductor silicon substrate. Then, a bottom electrode, a thin dielectric layer and a first top electrode layer are sequentially deposited on the surface of the field oxide layer. Next, a photoresist layer is coated on the surface of the first top electrode layer. Then, the first top electrode layer is patterned to form a top electrode stud. Next, a layer of silicon dioxide (SiO.sub.2) is deposited by Liquid Phase Deposition (LPD) to improve the overall profile of the antifuse structure. Thereafter, the photoresist pattern is removed. Next, a second top electrode layer is deposited overlaying the LPD-SiO.sub.2 layer and the top electrode stud. The top electrode that consists of the second top electrode layer and the top electrode stud is completed. The antifuse structure of FPGAs is accomplished.

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