Method to form an inverted staircase STI structure by...

Details Method to form an inverted staircase STI structure by... Method to form an inverted staircase STI structure by...

2002-01-03

2002-10-08

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Groove formation

C438S432000, C438S442000, C438S637000, C438S701000

Reexamination Certificate

active

06461887

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to forming isolation structures in semiconductor devices, and more specifically to methods forming shallow trench isolation regions (STI) in semiconductor devices.
BACKGROUND OF THE INVENTION
Latchup has been a concern for most of the complementary metaloxide semiconductor (CMOS) technologies. Latchup is a parasitic circuit effect, the result of which is the shorting of the VDD and Vss lines that usually results in chip self-destruction or at least system failure with the requirement to power down. Latchup effects will become severe when the VLSI circuit dimension is scaled. There are currently various ways to improve the latchup immunity by transistor design.
U.S. Pat. No. 5,681,776 to Hebert et al. describes selective epitaxial growth (SEG) active areas formed on an opening in an oxide layer.
U.S. Pat. No. 4,900,692 to Robinson describes epitaxial silicon (epi) active areas in a trench.
U.S. Pat. No. 5,212,110 to Pfiester et al. describes an epi active growth area.
U.S. Pat. No. 5,773,351 to Choi describes an SEG active area formed on an opening in an insulation layer.
U.S. Pat. No. 4,886,763 to Suzuki describes a process for forming EPI active areas between isolation areas.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of reducing latchup effect in adjacent semiconductor devices.
Another object of the present invention to provide a method of reducing latchup effect in adjacent semiconductor devices by increasing the distance between the n
+
S/D area of one semiconductor device to the p
+
S/D area of an adjacent semiconductor device.
Another object of the present invention to provide a method of reducing latchup effect in adjacent semiconductor devices by increasing the distance between the n
+
S/D area of one NMOS semiconductor device, for example, to the p
+
S/D area of an adjacent PMOS semiconductor device, for example, without sacrificing the isolation and the real estate.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas. The STI region comprising an inverted staircase shaped STI structure. The step side wall spacers are removed from the X+2 step trenches. A planarized active area silicon structure is formed within the X+2 and final step trenches.


REFERENCES:
patent: 4495025 (1985-01-01), Haskell
patent: 4886763 (1989-12-01), Suzuki
patent: 4900692 (1990-02-01), Robinson
patent: 5212110 (1993-05-01), Pfiester et al.
patent: 5298450 (1994-03-01), Verret
patent: 5663091 (1997-09-01), Yen et al.
patent: 5681776 (1997-10-01), Hebert et al.
patent: 5773351 (1998-06-01), Choi
patent: 5854140 (1998-12-01), Jaso et al.
patent: 5869395 (1999-02-01), Yim
patent: 5926732 (1999-07-01), Matsuura
patent: 5940731 (1999-08-01), Wu
patent: 6017817 (2000-01-01), Chung et al.
patent: 6171967 (2001-01-01), Jun
patent: 6207532 (2001-03-01), Lin et al.

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