Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-01-25
2001-11-06
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S296000, C438S433000, C257S510000
Reexamination Certificate
active
06313008
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the processes for forming field isolations or shallow trench isolation (STI).
2) Description of the Prior Art
The method of local oxidation of silicon(LOCOS) to form field oxide isolation around semiconductive devices built into the surface of silicon wafers has been practiced for over twenty-five years and has been adapted to many specific applications. In the process, a non-oxidizable mask of silicon nitride is formed over a thin layer of pad oxide grown on a blank silicon wafer. The mask is patterned by well known photolithographic methods and the wafer is oxidized, typically in steam, at temperatures in the neighborhood of 1,000° C. The mask is patterned so that, after oxidation, mesa like regions of silicon are surrounded by a region of silicon oxide insulation. The semiconductive devices are then formed on the silicon mesas. Over the years many problems with LOCOS have surfaced which have been addressed in a great variety of ways. Most notable are the problems which deal with the growth of oxide under the mask(birds beak) and the resultant uneven surface topology over the field oxide.
A promising replacement for LOCOS field oxide isolation has been found in trench isolation. Although deep trench isolation(DTI) has been used nearly as long as LOCOS for bipolar transistor isolation, it has not been widely practiced in the manufacture of MOSFET integrated circuits. More recently, however, as device densities increase and isolation widths become smaller, shallow trench isolation(STI) is gaining favor over LOCOS in MOSFET technology.
The trenches are formed in the silicon around the semiconductor devices by reactive ion etching. They are then filled either entirely with silicon oxide or lined with silicon oxide and filled with another material such as polysilicon.
A major problem the inventor's have realized, as the scale of the devices shrinks, the width/area of the STI at the chip surface is to large, thus using up valuable active area. In addition, the isolation of logic device is not good enough at a feature size less than 0.18 &mgr;m using conventional STI because the STI is too narrow below the wafer surface.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,688,044(Ohno) shows dope by I/I and isotropic etch.
U.S. Pat. No. 6,004,864(Huang et al.) show an isolation process.
U.S. Pat. No. 5,629,226(Ohtsuki) shows a trench etch, dope and etch.
U.S. Pat. No. 5,943,581(Lu et al.) shows an isotropic etch of a doped area to form a round trench.
U.S. Pat. No. 6,020,250(Kenney) shows a process for horizontal trenches.
U.S. Pat. No. 5,972,758(Liang) shows a STI trench.
U.S. Pat. No. 5,112,771(Ishii et al.) shows a round STI trench.
U.S. Pat. No. 5,432,365(Chin et al.) shows a shaped trench for a capacitor.
U.S. Pat. No. 4,853,348(Tsuboushi et al.) shows a shaped trench for a capacitor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a balloon shaped shallow trench isolation (STI).
It is an object of the present invention to provide a method for fabricating a balloon shaped shallow trench isolation (STI) where the top of the STI is narrower than the lower portions of the STI so that active areas is conserved and isolation is improved.
It is an object of the present invention to provide a method for fabricating a balloon shaped shallow trench isolation (STI) for CMOS devices with feature sizes less than 0.18 &mgr;m.
To accomplish the above objectives, the present invention provides a method of manufacturing a STI having a balloon shape.
The invention describes three preferred embodiments of methods for forming a balloon shaped STI trench.
A first general embodiment of the invention of a method of fabricating a balloon shaped shallow trench isolation (STI); comprising the following steps. A barrier layer is formed over a substrate. We form an isolation opening in said barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a doped region. The doped region is selectively etching to form a hole. The hole is filled with a insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions.
The second embodiment differs from the first embodiment by forming a trench in the substrate before an ion implant.
The third embodiment forms a liner in the trench before optional Ion implantation.
It is a preferred option in all three embodiments that CMOS logic FET devices are formed on the active areas between the shallow trench isolation (STI). The inventor have found that the invention's Balloon shape STIs have an advantage in forming logic FET devices because the distance carriers have to travel to cause isolation failure is longer. In particular, logic devices with feature sizes less than 0.18 &mgr;ms (e.g., STI width and dimensions of gate and Source/drains are helped by the invention.
This is an important understanding because the prior art forms memory devices with unusual shaped STI structures, but form memory devices and do not specifically form logic devices.
Another critical feature of the invention is that the STI region is narrower at the top (near the substrate surface) than below the surface (more than 0.2 &mgr;m below). For example, the balloon shaped shallow trench isolation (STI) regions is narrower at a depth of about 0.1 &mgr;m (.e.g., near the surface) between the surface of the substrate than at the at a depth of about 0.2 &mgr;m.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 4533430 (1985-08-01), Bower
patent: 4853348 (1989-08-01), Tsubouchi et al.
patent: 5112771 (1992-05-01), Ishii et al.
patent: 5432365 (1995-07-01), Chin et al.
patent: 5629226 (1997-05-01), Ohtsuki
patent: 5668044 (1997-09-01), Ohno
patent: 5915192 (1999-06-01), Liaw et al.
patent: 5943581 (1999-08-01), Lu et al.
patent: 5972758 (1999-10-01), Liang
patent: 6004864 (1999-12-01), Huang et al.
patent: 6020250 (2000-02-01), Kenney
patent: 6232202 (2001-05-01), Hong
patent: 6251750 (2001-06-01), Lee
patent: 000413040A1 (1991-02-01), None
patent: WO 01/29897 A1 (2001-04-01), None
Chan Lap
Lee James Yong Meng
Leung Ying Keung
Pan Yang
Pradeep Yelehanka Ramachandramurthy
Blum David S
Bowers Charles
Chartered Semiconductor Manufacturing Inc.
Pike Rosemary L. S.
Saile George O.
LandOfFree
Method to form a balloon shaped STI using a micro machining... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to form a balloon shaped STI using a micro machining..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to form a balloon shaped STI using a micro machining... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2595119