Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-03-12
2004-10-26
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S388000, C438S422000
Reexamination Certificate
active
06809005
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices, and, more particularly, to semiconductor trench structures having fill material of, e.g., silicon or polycrystalline silicon.
Semiconductor devices are employed in various systems for a wide variety of applications. Device fabrication typically involves a series of process steps including layering materials on a semiconductor substrate wafer, patterning and etching one or more of the material layers, doping selected layers and cleaning the wafer.
Semiconductor manufacturers continually seek new ways to improve performance, decrease cost and increase capacity of semiconductor devices. Capacity and cost improvements may be achieved by shrinking device size. For example, in the case of a dynamic random access memory (“DRAM”) chip, more memory cells can fit onto the chip by reducing the size of memory cell components such as capacitors and transistors. The size reduction results in greater memory capacity for the chip. Cost reduction is achieved through economies of scale. Unfortunately, performance can suffer when device components are shrunk. Therefore, it is a challenge to balance performance with other manufacturing constraints.
One method of shrinking device size is to vertically construct the components, either in a stack over the semiconductor substrate or within the substrate itself. One way to accomplish such vertical construction within the substrate involves forming a trench in the substrate. By way of example only, a capacitor may be fabricated within a trench. Such a capacitor is known as a “trench capacitor.”
The capacitor stores charge and includes a pair of electrodes separated by a dielectric material. The charge can represent a data value for use in a memory cell, such as a DRAM cell. While it is desirable to shrink the surface area of a trench capacitor to increase memory cell density, the trench capacitor must be able to store a sufficient amount of charge. For example, regardless of size, a trench capacitor of a DRAM cell requires a charge on the order of 25-30 fF (femto Farads). Therefore, it is imperative that trench capacitors be able to store sufficient charge. This may be accomplished by creating trenches which extend relatively deep into the substrate.
A conventional trench capacitor is typically formed as follows. First, a trench is etched in the substrate. The trench has sidewalls defined by surrounding portions of the substrate. Then, an outer electrode, a “buried plate,” is formed by implanting a dopant in the substrate surrounding the trench. Next, a dielectric liner, the “node dielectric,” is formed along the sidewalls, covering the outer electrode. Subsequently, an inner electrode is deposited within the trench. The inner electrode typically consists of polycrystalline silicon, also known as “polysilicon” or “poly-Si.”
In conventional processing, the trench is formed relatively deep within the substrate. For example, a “deep trench” may extend between 4-8 &mgr;m below the substrate surface at a given stage in the fabrication process. Deep trenches are typically high aspect ratio trenches. The “aspect ratio” is the ratio of the depth of a trench compared to the width of the opening at the top of the trench. By way of example only, high aspect ratio trenches in advanced semiconductor manufacturing may have an aspect ratio of between 20:1 and 60:1 or higher.
A high aspect ratio trench adversely impacts formation of the inner electrode. This is so because of how the inner electrode is formed. The poly-Si inner electrode is formed by a deposition process such as chemical vapor deposition (“CVD”). For example, an ultra high vacuum (“UHV”) CVD process may be used, wherein the pressure is below 1×10
−7
Torr. During deposition, the poly-Si grows inward from the sidewalls. However, this process typically creates voids, gaps or seams within a central portion of the inner electrode.
FIG. 9
illustrates a conventional trench capacitor
430
having a void
422
. A trench
406
has been formed into the substrate
400
. A pad stack
402
comprised of a pad oxide
402
a
and a pad nitride
402
b
covers the surface of the substrate
400
. The sidewalls
404
of the trench
406
extend through the pad stack
402
into the substrate
400
. A lower portion of the sidewalls
404
are covered with a node dielectric
410
, and an upper portion of the sidewalls
404
are covered by an oxide collar
408
. An outer dielectric
412
is formed within the substrate
400
adjacent to the node dielectric
410
. An inner electrode
420
of poly-Si is formed within the trench
406
. As described above, conventional deposition of the poly-Si typically produces the void
422
(or gap or seam) within the inner electrode
420
. The void
422
increases the resistance of the trench capacitor
430
, which can adversely affect its performance. Furthermore, the void
422
typically increases the difficulty of later processing of the conventional trench capacitor
430
. For example, the poly-Si within the trench
406
may be recessed or etched back to a desired depth below the surface of the substrate
400
. The void
422
may render this recessing step unpredictable in terms of, e.g., etch rate, depth and width. If the void
422
is within the etch range during poly-Si recessing or etch-back, e.g., approximately 1.3-1.5 &mgr;m below the pad oxide
402
a
and substrate
400
interface, then the recessing or etch-back depth may become uncontrollable. In such a case, the etching/recessing could leave a prominent “V” shape at the bottom of the recessed trench. Then, when the collar
408
is deposited, it could be deposited in the void. Subsequent processing would not remove oxide that remains in the void, which leads to increased contact resistance between the layers of poly-Si deposited to form the inner electrode
420
. Furthermore, the presence of the void
422
may create a non-planar surface for the inner electrode
420
, thereby affecting later fabrication steps.
Creating a trench having a tapered top can reduce void formation, because the tapered top allows the deposition process better access to the trench, resulting in more complete fill. Generally, increasing the taper angle, e.g., widening the trench opening, reduces void formation. However, larger taper adversely affects the “effective” trench depth (i.e., the depth of the trench excluding the tapered portion).
A void is revealed by etching through the poly-Si until the void is exposed. The void is typically healed by depositing poly-Si into the void after the collar oxide is formed. However, large voids often cause problems such as poor depth control of the healing deposition process. As such, the deposition of poly-Si within long voids running substantially the depth of the trench may not sufficiently heal the defect.
Thus, new methods of formation of capacitor inner electrodes, as well as formation of other fill materials, are desired. The methods should minimize or eliminate void formation in filled trench structures. Improved methods of healing pre-existing voids are also desired.
SUMMARY OF THE INVENTION
The present invention provides methods of forming substantially void-free fillers in trench structures. It is to be appreciated that the numbers used (by way of example only, temperature, time and pressure) are approximations and may be varied, and certain steps may be performed in different order.
In accordance with one embodiment of the present invention, a method of fabricating a semiconductor device is provided. The method comprises first forming a trench having sidewalls in a semiconductor substrate. Next, a liner is deposited over the sidewalls. Then, a filler is grown within the trench from the liner. Preferably, the liner is polysilicon. Also, the filler may be grown in a non-selective manner. Optionally, the method may include removing a native oxide from an exposed surface of the liner prior to growing the filler.
In accordance with another embodiment of the present invention, a method of fabricating a semiconductor d
Chan Kevin K.
Kulkarni Subhash B.
Mathad Gangadhara S.
Ranade Rajiv
Infineon - Technologies AG
Lee Calvin
Lerner David Littenberg Krumholz & Mentlik LLP
Smith Matthew
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