Method to fabricate SiGe HBTs with controlled current gain...

Details Method to fabricate SiGe HBTs with controlled current gain... Method to fabricate SiGe HBTs with controlled current gain...

2003-10-01

2004-09-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S342000

Reexamination Certificate

active

06787427

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to heterojunction bipolar transistors (HBTs), and more particularly to a method of fabricating SiGe HBTs which exhibit controlled current gain and improved breakdown voltage. The present invention is also directed to a SiGe HBT structure which includes a bilayer of in-situ phosphorus (P)-doped amorphous silicon (a:Si) and in-situ P-doped polysilicon as the emitter.
BACKGROUND OF THE INVENTION
Significant growth in both high-frequency wired and wireless markets has introduced new opportunities where compound semiconductors such as SiGe have unique advantages over bulk complementary metal oxide semiconductor (CMOS) technology. With the rapid advancement of epitaxial layer pseudomorphic SiGe deposition processes, epitaxial-base SiGe heterojunction bipolar transistors have been integrated with mainstream advanced CMOS development for wide market acceptance, providing the advantages of SiGe technology for analog RF (radio frequency) circuitry while maintaining the utilization of the advanced CMOS technology base for digital logic circuitry.
In a conventional emitter polysilicon process, the current gain beta, Ic/Ib, is controlled by depositing a thin interfacial oxide layer prior to deposition of the polysilicon emitter. This thin oxide layer is employed as a minority carrier barrier to reduce base current (Ib) and to increase current gain. As this interfacial oxide layer becomes very thin, the thickness uniformity of the oxide becomes an issue. Specifically, as the interfacial oxide becomes thin, the oxide layer has a non-uniform thickness which causes beta variation. In view of the above drawbacks with prior art emitter polysilicon processes, there is a continued need for providing a process of fabricating SiGe HBT which is capable of controlling the current gain without the worry of oxide thickness non-uniformity issues.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a SiGe HBT which has a controllable current gain associated therewith.
A further object of the present invention is to provide a method of fabricating a SiGe HBT which has improved breakdown voltage characteristics associated therewith.
A yet further object of the present invention is to provide a method of fabricating a SiGe HBT which has a low beta, i.e., collector current Ic/base current Ib, associated therewith.
These and other objects and advantages are achieved in the present invention by utilizing a method wherein the emitter is formed by an in-situ P-doped deposition processing step.
Specifically, the method of the present invention comprises:
forming an emitter layer atop a patterned SiGe base structure, wherein said emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon.
In some embodiments of the present invention, an oxide layer is formed atop exposed portions of the single crystal SiGe base region of the patterned SiGe base structure prior to forming the emitter layer. In yet other embodiments of the present invention, the in-situ P-doped a:Si layer is annealed after its formation.
Another aspect of the present invention relates to a SiGe HBT structure which comprises
a patterned SiGe base structure which includes at least a SiGe layer present atop a substrate and a patterned insulator present atop the SiGe layer having an opening that exposes a portion of said SiGe layer; and
an emitter layer formed atop said SiGe base structure including in said opening, said emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon.


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