Method to fabricate high-performance NPN transistors in a...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Mesa structure

Reexamination Certificate

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C257S624000, C257S626000

Reexamination Certificate

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06906401

ABSTRACT:
A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

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