Method to fabricate Ge and Si devices together for...

Details Method to fabricate Ge and Si devices together for... Method to fabricate Ge and Si devices together for...

2007-04-10

2007-04-10

Hoang, Quoc (Department: 2818)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S667000, C257S621000, C257SE21088

Reexamination Certificate

active

11297540

ABSTRACT:
A method for forming a semiconductor structure having devices formed on both sides. A first substrate and a second substrate are provided. The first substrate is preferably comprised of Ge. The second substrate is preferably comprised of silicon. We form a first dielectric layer over the first substrate. We form a first insulating layer over the second substrate. We bond the first dielectric layer and the first dielectric layer to form a first structure. The first structure comprised of the first substrate, an insulation layer (combined first dielectric and first insulating layers) and the second substrate. We reduce the thickness of the first substrate. We form via plugs through the first substrate and the insulation layer and at least partially through the second substrate. We form first active devices on the surface of the first substrate. We form a first capping layer over the first active devices and the first substrate. We reduce the thickness of the second substrate to expose the via plugs. We form second active devices on the second substrate.

REFERENCES:
patent: 6150708 (2000-11-01), Gardner et al.
patent: 6194290 (2001-02-01), Kub
patent: 6451634 (2002-09-01), Ma et al.
patent: 6774010 (2004-08-01), Chu et al.
patent: 6774447 (2004-08-01), Kondo et al.
patent: 7101773 (2006-09-01), Danel
patent: 2002/0195602 (2002-12-01), Klosowiak
patent: 2004/0072409 (2004-04-01), Fitzgerald et al.
patent: 2004/0084720 (2004-05-01), Esser et al.
patent: 2004/0106268 (2004-06-01), Shaheen et al.
patent: 2004/0137698 (2004-07-01), Taraschi et al.
Chow, et al., Process Compatible Polysilicon-Based Electrical Through-Wafer Interconnects in Silicon Substrates, Journal of Microelectromechanical Systems, vol. 11, No. 6, Dec. 2002 631. discusses using wafer bonding in combination with thru wafer interconnects.
Laura Peters, Wafer Bonding Enables New Technologies and Applications, Nov. 1, 2003 Semiconductor International , http://www.reed-electronics.com/semiconductor/index.asp?layout=articlePrint&articleID=CA331034.—discusses various wafer bonding techniques and applications.
Moon, J.S. ; Simmons, J.A. ; Wendt, J.R. ; Hietala, V.M. ; Reno, J.L. ; Baca, W.E. ; Blount, M.A., Title Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications, Publication Date Jul. 20, 1999, OSTI Identifier OSTI ID: 9577 website: http://www.osti.gov/bridge/servlets/purl/9577-hwRMde/webviewable/9577.pdf.

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