Method to fabricate electrodes for high-K dielectrics

Details Method to fabricate electrodes for high-K dielectrics Method to fabricate electrodes for high-K dielectrics

1999-03-10

2001-03-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S240000

Reexamination Certificate

active

06207525

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor manufacturing process. More specifically, the present invention relates to a method for fabricating electrodes, especially the electrodes incorporating the use of high-k dielectrics to form capacitors.
BACKGROUND OF THE INVENTION
In last four decades, the semiconductor industry has been developed continuously to fabricate integrated circuits with highly effective and densely packed devices. In the application of integrated circuits, memory chips is one of the most important chips in the application of electronic products. With the fast growth of computer, communication, and consumer electronic devices, the need for high density and low cost memory chips, either volatile memories like DRAMs (dynamic random access memories) and SRAMs (static random access memories) and nonvolatile memories like flash memories, is increasing quickly for improving the functions of the devices. Typically, a single chip may include more than a million or even a billion devices to expand memory capacity or functional characteristics of integrated circuits. Taking DRAMs as an example, the capacity of a single chip has been raised from 16 megabytes, 64 megabytes to 256 megabytes or even higher capacities.
Typically, the construction of a DRAM cell mainly includes a operating transistor and a storage cell composed mainly of a capacitor. For increasing the device density of memory cells in an unit area, the size of the operating transistor and the capacitor must be reduced without damaging the operational characteristics and the storage capacity of the capacitor. Several different methods, such as the reconstruction of the storage electrode and the selection of the materials of the electrode and dielectrics, had been proposed to increase the storage capacity of a small size cell.
In the present stage technology of semiconductor fabrication, dielectrics with high dielectric constant, or namely high k dielectrics, are employed in the fabrication of both volatile and non-volatile memory cells to improve their functional characteristics. High k dielectrics such as barium strontium titanate (BST) and lead zirconate titanate (PZT) are well known to be good candidates for DRAM higher than 4 gigabyte and high density, highly capacitive non-volatile memories. Electrode materials such as platinum (Pt), Ruthenium oxide (RuO
2
), Iridium oxide (IrO
2
) and etc. can be used in combination with aforementioned high k dielectrics for providing improved capacitive effects.
However, the aforementioned electrode materials are not the commonly used electrode materials like polysilicon, titanium, and aluminum-based metals employed in present stage semiconductor fabrication. The etching chemistry, control and contamination problems are considered as some of the obstacles in the application of these newly-employed materials. As an example, traditional platinum etching process for defining prescribed patterns was typically suffered from the contamination and control problems of volatile platinum etching byproducts, and also the resulting problem of poor CD (critical dimension) control.
In addition to the selection of conductive materials and dielectrics, another approach to increase the performance of DRAM cell is by increasing surface area of electrodes to increase storage capacity. One of conventional approaches on increasing the surface area of electrodes is to re-construct the shape of the major electrode, or namely the bottom electrode, in order to increase the surface area with the re-constructed shape like extended fins or the application of hemispherical grains of polysilicon. However, the newly-employed materials like platinum (Pt), Ruthenium oxide (RuO
2
), Iridium oxide (IrO
2
) and etc., under the limitation in etching control, are hard to define with complex shapes. The increase of surface area of these newly-employed materials are further limited with the hardness in shape definition.
SUMMARY OF THE INVENTION
The present invention is directed to a method to fabricate electrode for high-k dielectrics. The method proposed herein, with the shape defining layer without employing traditional etching processes, enables good critical dimension control in defining the shape and size of electrical nodes for capacitor cells. In the preferred embodiments of the present invention, the surface area of the electrodes is further increased with the control of chemical mechanical polishing and processing slurries.
A method in the invention for fabricating electrodes on a semiconductor substrate includes the following steps. After a first step forming a node-defining layer on the substrate, a subsequent step of patterning the node-defining layer is carried out to form a plurality of node openings within the node-defining layer. A first conductive layer is formed to fill into the openings and to form over the node-defining layer. A step of removing a portion of the first conductive layer is performed to remove the portion which is located outside the openings. Finally, a step of removing the node-defining layer is done to leave a plurality of first electrodes.
In addition to the aforementioned steps of forming the first electrodes, two more steps may be added to finish the formation of capacitor cells. At first, a dielectric layer is formed over the first electrodes after the removal of the node-defining layer. A subsequent step of forming a second conductive layer is carried out to form the second conductive layer over the dielectric layer, with preferably the same material as the first electrodes.


REFERENCES:
patent: 5998225 (1999-12-01), Crenshaw et al.

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