Method to fabricate a semiconductor memory device having an E-sh

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 2170, H01L 2700

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active

056041462

ABSTRACT:
A method is described for forming a dynamic random access memory cell with an increased capacitance capacitor. Device structures, including a capacitor node contact region, are formed in and on the semiconductor substrate. A dielectric layer and a thick insulating layer are deposited over the device structures and planarized. A contact is opened to the capacitor node contact region. A first layer of polysilicon is deposited filling the contact opening. The portion contacting the node contact region forms the bottom electrode of the capacitor. A portion of the polysilicon layer is etched away to form a well above the contact opening. A layer of silicon oxide is deposited within the well and is etched back to leave spacers on the sidewalls of the well. A second layer of polysilicon is deposited over the first polysilicon layer and within the well. The second polysilicon layer is removed except where it forms a plug within the well. The spacers are removed leaving gaps on either side of the plug. The first polysilicon layer is patterned so that an E-shaped storage node structure having three prongs pointing upward is formed. The plug forms the central prong and the outer two prongs are formed by the patterned first polysilicon layer. A capacitor dielectric layer is deposited over all surfaces of the E-shaped structure. A third polysilicon layer is deposited over the capacitor dielectric covering and filling the gaps of the E-shaped structure and forming the top capacitor electrode.

REFERENCES:
patent: 5340763 (1994-08-01), Dennison
patent: 5354705 (1994-10-01), Mathews et al.
patent: 5364809 (1994-11-01), Kwon et al.
patent: 5389568 (1995-02-01), Yun
patent: 5418180 (1995-05-01), Brown
patent: 5438013 (1995-08-01), Kim et al.

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