Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1997-10-01
2001-05-22
Couso, Jose L. (Department: 2721)
Image analysis
Applications
Manufacturing or product inspection
C382S294000
Reexamination Certificate
active
06236746
ABSTRACT:
This invention relates to the field of semiconductor integrated circuit structure analysis.
BACKGROUND OF THE INVENTION
In the intensely competitive field of microelectronics, detailed analysis of a semiconductor integrated circuit product can provide valuable information as to how a particular technical problem was dealt with, overall strengths and weaknesses of a design approach etc. This information can be used to make decisions regarding market positioning, future designs and new product development. The information resulting from analysis of the product is typically provided through circuit extraction (reverse engineering), functional analysis and other technical means. At the core of this activity is the process of design analysis which, in this context, refers to the techniques and methodology of deriving complete or partial schematics, starting with essentially any type of integrated circuit in any process technology. For such technical information to be of strategic value it must be accurate and cost-effective, and it is very important that the information should be timely.
A design analysis process typically involves skilled engineers manually extracting circuit information from a set of large “photomosaics” of an integrated circuit (IC). Skilled technicians and engineers perform the following sequential manual tasks:
(1) Capture Image:
(i) a high magnification photograph is taken, using a camera, of a small portion of an IC which has been processed to expose a layer of interest.
(2) step (i) is repeated for all of various regions of interest of the layer of the IC, ensuring that sufficient overlap exists between adjacent photographs that will be used to create photomosaics.
(3) Create Photomosaics:
(ii) all adjacent photographs associated with the given IC layer are aligned and taped together.
(4) steps (1)-(3) are repeated for all layers (I)-(N) necessary to construct a complete visual representation of the IC layers. All layers include interconnect layers. For example, foul sets of photomosaics are required for a state-of-the-art microprocessor employing four layers of interconnect: three layers of metal and one layer of polysilicon.
(5) Extract Circuit:
(iii) transistors, logic gates and other elements employed in the IC are identified by manually visually examining the polysilicon and lower metal interconnect photomosaics.
(iv) interconnections between circuit elements of (iii) are traced and this information is captured in the form of schematic drawings.
(v) drawings of (iv) are manually checked against the photomosaics and any obvious errors are corrected.
(6) Organize Schematic:
(vi) the drawings of (v) are organized into hierarchial functional/logical blocks.
(7) Capture Schematic:
(vii) the drawings of (vi) are entered into a computer using computer aided engineering (CAE) software tools for subsequent simulation and functional analysis of the IC.
The aforenoted manual process used today has major limitations. The photomosaics alone for devices of current complexity are very expensive and can take many months to create. The circuit extraction task is labour intensive, tedious and error-prone. As IC device geometrics shrink toward 0.1 micron and levels of integration move toward the equivalent of 1 billion transistors on a single device, the current manual process for full-chip design analysis will become impractical.
In order to overcome the above-described manual process, automated systems have been designed. Such systems are described in U.S. Pat. No. 5,086,477 issued Feb. 4, 1992 to Kenneth K Yu et al and U.S. Pat. No. 5,191,213 issued Mar. 2, 1993 to Haroon Ahmed et al. and also U.S. patent application Ser. No. 08/420,682.
In the system described in U.S. Pat. No. 5,086,477, the integrated circuit chip is scanned by a microscope or scanning electron microscope (SEM). The system identifies every unique cell and/or gate used in the integrated circuit. A unique abstract representation is created for each of these unique cells or gates, which are stored in a library.
However, without any operator guidance, the system cannot know where the boundary of a cell lies. While the patent suggests the use of diffusion edges to define cell boundaries, it appears that the only way that this can be done is by manual operator direction.
In the patented system, once all unique cells have been captured in a reference library, the system attempts to associate and match all abstract features contained in the layout data base to the cells in the reference library using classical template matching. However because of the magnitude of data contained in a layout data base for a typical modern integrated circuit, even after the data has been compressed, the processing time required to reliably extract a netlist is large. The difficulty and time required for the operator directed process becomes very difficult with a large number of cells or gates, since the number of template matching operations increases exponentially with the number of reference cells and/or gates.
Once all reference cells in the patented system have been template matched to the data base, theoretically all features in the layout data base will have been grouped and classified and a netlist can be constructed. If all the features of the layout data base have been classified then a netlist can be constructed. If there are features of the layout data base that have not been classified, either the system must construct a new cell or gate to be added to the reference library and an operator is informed, or the operator is informed by the system and the operator performs this task. The cell to cell interconnect information extraction, which is required to construct a netlist, is said to be performed using template matching, which is very inefficient.
Due to the template matching approach that is required, the patented system should be limited to gate-array or very structured standard cell integrated circuit analysis in which the large majority of the cells are identical, since as the number of cells in the integrated circuits increase, the efficiency decreases. It is therefore inefficient for analysis of modem ASICs or custom integrated circuits, large and/or complex integrated circuits. The patented system would also be limited to applications where many devices from a few ASIC manufacturers are investigated, due to the investment and time required to develop separate reference libraries, e.g. related to a different set of design rules.
U.S. Pat. No. 5,191,213 relates to a technique for removing layers of an integrated circuit and for scanning each of the layers.
U.S. Pat. No. 5,694,481 discloses a system which performs the following steps, in the following order: a) image capture; b) image segmentation and polygon generation; c) registering (of polygon data); d) vertical alignment; e) schematic generation. Although an improvement over the prior art this technique still has its limitations, some of them being:
1. Segmentation and polygon generation results are degraded around the boundaries of each of the images, which increased the amount of operator interaction. This could be minimized, by decreasing the perimeter to area ratio of the size of each image being captured. This minimizes the problem without solving the source.
2. Registering of polygon data is not as precise as registering of images, Although a saving is generated in terms of computing time, operator time, especially at the vertical alignment phase is increased.
3. Vertical alignment employes a potentially large search to align the different IC lavers to each other. This search involves aligning sets of contacts and vias to each other from successive layers. This task could be hampered by a number of reasons:
i. If deprocessing was poor, contacts/vias would not necessarily be easily replicated from layer-to-layer. Contacts/vias from successive layers may not necessarily be available.
ii. The preferred embodiment of that invention used an SEM to perform image capture. Any SEM magnification drift could not be accommodated in the previous disclosure.
i
Chamberlain George
Ioudovski Alexi
Naim Ghassan
Thomas John-Scott
Couso Jose L.
Dang Duy M.
Semiconductor Insights Inc.
Sterne Kessler Goldstein & Fox P.L.L.C.
LandOfFree
Method to extract circuit information does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to extract circuit information, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to extract circuit information will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2547465