Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-02-20
2004-02-24
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S763000
Reexamination Certificate
active
06696761
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to interconnection structures for silicon semiconductor devices and more particularly to methods and apparatus for forming conductive plugs serving as contacts or via connections.
2. Description of Related Art
U.S. Pat. No. 5,674,787 of Zhao et al. for “Selective Electroless Copper Deposited Interconnect Plugs for ULSI Applications” shows selective electroless deposition of copper in a via hole using a seed layer. An electroless copper (Cu) deposition method selectively forms encapsulated copper plugs to connect conductive regions of a semiconductor device. A contact displacement technique forms a thin activation copper layer on a barrier metal layer, e.g. TiN, which covers the underlying metal layer. Copper is deposited in the via by an electroless auto-catalytic process. Electroless copper deposition continues until the via is almost filled which leaves sufficient room at the top for an upper encapsulation to be formed there, but first the device is rinsed in DI water to remove the electroless deposition solution. Then after the rising away of the electroless copper solution, a cap barrier layer, from 500 Å to about 1500 Å thick, is formed of a variety of metals or metal alloys such as Ni, Co, Ni—Co alloy, CoP, NiCoP, or NiP from another electroless solution. Sidewalls of SiN or SiON, the bottom barrier layer and the cap barrier layer complete the full encapsulation of the copper plug via.
U.S. Pat. No. 5,470,789 of Misawa for “Process for Fabricating Integrated Circuit Devices” produces TiN/Cu (titanium nitride/copper) wiring and contact layers each having a capping layer formed of TiN unlike the Pt, Pd, or Ag cap layer of this invention.
U.S. Pat. No. 4,282,271 of Feldstein for “Dispersions for Activating Non-Conductors for Electroless Plating” shows an electroless deposition technique.
SUMMARY OF THE INVENTION
Alternative metallization metal that is capable of delivering better (1) conductivity and (2) minimizing electromigration is implemented in a design in accordance with this invention. Copper is very much envisaged to be the future metal for interconnect metals in vias and contacts since it meets the above two important criteria. Moreover, deposition of copper by the electroless method seems to be an attractive approach based upon factors such as cost of ownership, simplicity of the process and void-free filling capability. However, copper is very prone to oxidation and degradation unless proper treatment is carried out after deposition. Such oxidation and degradation adversely affect the overall performance of devices.
In accordance with this invention, a method is provided for forming a copper plug on a doped silicon semiconductor substrate having a substrate surface which is covered with an insulation layer which comprises the following steps. Form a plug hole in the insulation layer down to the substrate surface, which plug hole has walls and a bottom comprising a portion of the substrate surface. Form a diffusion barrier on the walls and the bottom of the hole. Partially fill the plug hole with a copper metal deposit to a predetermined depth which is less than the depth “h” of the hole leaving a space in the plug hole above the copper metal deposit. Deposit an encapsulating metal layer on the surface of the copper metal deposit including an overgrowth above the plug hole, and then polish the surface of the insulator layer removing the overgrowth of the metal layer to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.
Preferably, the copper metal deposit is plated in an enclosed environment, such as a plating process which preferably employs an electroless plating bath. After the predetermined depth been reached, the plating continues, gradually switching the constituents in the bath from copper to codeposition of copper and the encapsulating layer followed by plating, preferably electrolessly, only the encapsulating metal layer from the bath into the space at the top of the plug hole above the copper metal deposit and then after filling the plug hole, the plating continues until a small overgrowth has been formed.
Preferably, the encapsulating metal layer is composed of a noble metal, preferably selected from the group consisting of Pt, Pd, and Ag, and the encapsulating layer is then polished by a CMP process after the overgrowth.
Preferably, the diffusion barrier layer is composed of a refractory metal nitride selected from the group consisting of TiN, TaN and WN.
In accordance with another aspect of this invention, a device including a doped silicon semiconductor substrate has a substrate surface which is covered with an insulation layer in which a copper plug is formed in contact with the substrate surface. There is a plug hole in the insulation layer down to the substrate surface, the plug hole having walls and a bottom comprising a portion of the substrate surface. A diffusion barrier is formed on the walls and the bottom of the hole. A copper metal deposit partially fills the plug hole to a predetermined depth which is less than the depth “h” of the hole leaving a space in the plug hole above the copper metal deposit formed in situ with an encapsulating metal layer deposited on the surface of the copper metal deposit. The surface of the insulator layer had been polished to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer. Thus, the space at the top of the plug hole is covered with pure encapsulating metal at the top of the hole without any copper.
Preferably, the copper metal plug was deposited in situ to the predetermined depth less than the depth “h” was reached with a gradual transition of a codeposit of the copper metal and the encapsulating metal layer in the space in the plug hole above the copper metal deposit until only the encapsulating metal is present without any of the copper at the top of the plug hole.
Preferably the copper was deposited by plating, preferably in a plating bath, in an enclosed environment to the predetermined depth less than the depth “h” and gradually switched to a codeposit with the encapsulating metal layer into the space in the plug hole above the copper metal deposit until a small overgrowth of the metal layer has been formed above the plug hole.
The plating bath plates copper until the predetermined depth less than the depth “h” was reached with a gradual transition from of the constituents in the bath to plate the encapsulating metal layer from the bath.
Preferably, the copper metal deposit was plated from a plating bath in an electroless plating process.
Preferably, a gradual transition of the constituents in the bath to plate a codeposit of the copper and the encapsulating metal layer from the bath into the space in the plug hole to pure encapsulating metal at the top of the hole without any copper.
Preferably, the diffusion barrier layer is composed of a refractory metal nitride preferably selected from the group consisting of TiN, TaN and WN.
Preferably, the encapsulating metal layer is composed of a noble metal selected from the group consisting of Pt, Pd, and Ag.
REFERENCES:
patent: 4282271 (1981-08-01), Feldstein
patent: 5470789 (1995-11-01), Misawa
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5824599 (1998-10-01), Schacham-Diamand et al.
patent: 5898222 (1999-04-01), Farooq et al.
patent: 6147408 (2000-11-01), Ogure et al.
patent: 2002/0004302 (2002-01-01), Fukumoto
Chan Lap
Li Sam Fong Yau
Ng Hou Tee
Cao Phat X.
Chartered Semiconductor Manufacturing Ltd.
Jones II Graham S.
Pike Rosemary L. S.
Saile George O.
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