Method to eliminate gate filaments on field plate isolated devic

Details Method to eliminate gate filaments on field plate isolated devic Method to eliminate gate filaments on field plate isolated devic

1992-05-05

1993-10-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 48, 437 52, 437238, H01L 21306

Patent

active

052525066

ABSTRACT:
A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.

REFERENCES:
patent: 4888298 (1989-12-01), Rivaud et al.

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