Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – System-on-chip design
Reexamination Certificate
2007-10-10
2011-10-18
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
System-on-chip design
C716S111000, C716S112000, C716S113000, C716S126000, C370S235000, C370S293000
Reexamination Certificate
active
08042087
ABSTRACT:
A method to design a Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of modelling the applications running on the multicore system, establishing the number and configuration of switches to connect the elements, establishing physical connectivity between the elements and the switches, for each two pairs of communicating elements: (a) a defining a communication path, (b) calculating metrics as affected by the need to render said path into physical connectivity, taking into account any previously defined physical connectivity, (c) iterating the steps a and b for a plurality of possible paths, (d) choosing the path having the optimal metrics, and (e) establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically connected switches.
REFERENCES:
patent: 6968514 (2005-11-01), Cooke et al.
patent: 2006/0077914 (2006-04-01), Rhee
patent: 2006/0161875 (2006-07-01), Rhee
patent: 2009/0004981 (2009-01-01), Eliezer et al.
patent: 2009/0070549 (2009-03-01), Solomon
patent: 2010/0080124 (2010-04-01), Angiolini et al.
Meloni et al.; “Routing Aware Switch Hardware Customization for Networks on Chips”; Publication Year: 2006; Nano-Networks and Workshops, 2006. NanoNet '06. 1st International Conference on; pp. 1-5.
Chi-Ying et al.; “VLSI implementation of a switch fabric for mixed ATM and IP traffic”; Publication Year: 2000; Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific; pp. 5-6.
Kim et al.; A low latency router supporting adaptivity for on-chip interconnects; Publication Year: 2005; Design Automation Conference, 2005. Proceedings. 42nd; pp. 559-564.
Benini, L., “Application Specific NoC Design”, IEEE, pp. 1-5 (2006).
Sethuraman, B., et al., OptiMap: A Tool for Automated Generation of NoC Architectures Using Multi-Port Routers for FPGAs, IEEE, pp. 1-6 (2006).
Benini, L., et al., Networks on Chips: A New SoC Paradigm, IEEE Computers, pp. 70-78 (2002).
Bertozzi, D., et al., NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, vol. 16, No. 2, pp. 113-129 (2005).
Srinivasan, K., et al., ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis, IEEE, pp. 623-628 (2005).
Srinivasan, K., et al., A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures, IEEE, pp. 1-6 (2006).
Pasricha, S., et al., Constraint-Driven Bus Matrix Synthesis for MPSoC, IEEE, pp. 30-35 (2006).
International Search Report issued in PCT/IB2007/054122 dated Mar. 4, 2008.
Benini Luca
De Micheli Giovanni
Murali Srinivasan
DLA Piper (LLP) US
Ecole Polytechnique Federale De Lausanne (EPFL)
Rossoshek Helen
LandOfFree
Method to design network-on-chip (NOC)-based communication... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to design network-on-chip (NOC)-based communication..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to design network-on-chip (NOC)-based communication... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4291886